Chris_C Posted October 15, 2014 Report Share Posted October 15, 2014 After a fair break from almost everything electronic (thats what being a newly wed does for your "spare" time) I decided to get back into FPGA's Last time I got as far a VGA character generator in VHDL and concluded that the schematic route would probably suit me better! I does seem to bespite how aggravating ISE is ! (just don't get me started on BUS TAPS!!!!) anyhow I decided after getting the 32mhz clock downcounted to flash the led every 1/2 second, that I might look at input via USB my first instinct was to simply connect RX to TX which I did via a buffer - which works I get back what I send! (shocking!) however I get a warning that I'm not entirely comfortable with... WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp TX_PULLUP is set but the tri state is not configured. Now I do know what a pull up and tri state actually is BUT what I am wondering is how in the earth do you tell ISE what configuration you want for the tri state ( and why and whats needed for this circumstance) One the subject of USB serial, there is no clock?? if I want to read RX into an 8 bit buffer how do I know how long a bit is ?! Link to comment Share on other sites More sharing options...
offroad Posted October 15, 2014 Report Share Posted October 15, 2014 Hi, don't worry about that warning. It should disappear if your circuit is capable of outputting a "z" state (in Verilog), tristate, which stops driving the output.What ISE is trying to tell you is "hey, you've got that pull-up resistor there but it's never really doing anything because the output is driven all the time. Why don't you remove it and it will still cost the same"After a while, I stopped listening It is impossible to get rid of all warnings, as I would in software. Some of them simply don't make sense, such as "unconnected port" warning.My recommendation is to read the warnings when your circuit doesn't work as expected. It can be tedious.However, you can fix the pullup warning, simply by removing the "PULLUP" attribute from the constraints (*.ucf) file. ISE is an example of "tool hell". Still, it has its good sides - it's free up to Spartan 6 LX 75, and competitors' comparable offerings have limitations that go far beyond "annoying" (i.e. no access to memory controller without paid license). Link to comment Share on other sites More sharing options...
Chris_C Posted October 15, 2014 Author Report Share Posted October 15, 2014 Yeah I gettcha, thanks, any idea about USB serial input timings? Link to comment Share on other sites More sharing options...
TomKeddie Posted October 15, 2014 Report Share Posted October 15, 2014 The serial is async, the usb just tunnels the chars from the software driver and outputs them async. In the fpga need a uart, I used the kcuart from Ken Chapman in my xilinx work, seemed to work well for me. There are a lot of crappy implementations I found that make assumptions about the incoming signal.Google "ken chapman kcuart" I think link 4 is a zip file.i think you need to provided a divided clock to set the baud rate.Cheers,Tom Link to comment Share on other sites More sharing options...
Chris_C Posted October 15, 2014 Author Report Share Posted October 15, 2014 I was afraid it would be asynchronous.... I do so prefer serial data thats clocked! (call me lazy!) I'll take a look for your recommended uart - thanks Link to comment Share on other sites More sharing options...
Jack Gassett Posted October 16, 2014 Report Share Posted October 16, 2014 There is actually a Papilio project for Ken Chapman's high speed UART right here:http://papilio.gadgetfactory.net/index.php?n=Papilio.HighSpeedUART I will also be working it into the schematic library using the EDIF version of the files soon. Jack. Link to comment Share on other sites More sharing options...
Chris_C Posted October 16, 2014 Author Report Share Posted October 16, 2014 There is actually a Papilio project for Ken Chapman's high speed UART right here:http://papilio.gadgetfactory.net/index.php?n=Papilio.HighSpeedUARTI will also be working it into the schematic library using the EDIF version of the files soon.Jack.I did see that page....Alas clicking the YouTube links gets me to a 404 ! Link to comment Share on other sites More sharing options...
Jack Gassett Posted October 16, 2014 Report Share Posted October 16, 2014 Ooops, sorry about that, I updated the links. Jack. Link to comment Share on other sites More sharing options...
Chris_C Posted October 17, 2014 Author Report Share Posted October 17, 2014 Thanks! Link to comment Share on other sites More sharing options...
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