Generating DCM on Papilio Pro


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I'm following a tutorial called "Intro to Spartan FPGA" :

and I ran into a problem.


In chapter 18, we are supposed to generate a DCM. Unfortunately, this tutorial is written for Spartan 3, and all the options that are available under the clocking submenu in the CORE Generator are for Spartan 3. 

This means that I have no idea how to create a DCM on Spartan 6. I tried looking for answers on the internet, but the answers were far too technical and I didn't understand much of the content.


I was specifically trying to run this code, written by Hamster:

but it requires DCMs. Why he would need 2 of those is a whole new problem that i will try to take on when I actually get one of them working.


Maybe you know how to solve this problem?


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with ISE (14.7) and an open project, click "core generator" in the "Tools menu". The core generator window opens.

"File" menu, "new project", enter anynameyoulike.cgp.

"Project options" window opens.

Set family: "Spartan 6"

Device: "XC6SLX9"

Package tqg144

Speed grade "-2" (I think, if in doubt check with a magnifying glass what's written on the chip)

You could change to Verilog code generation, but the tutorial is for VHDL, which is default.

Click OK

Under "IP catalog", open "FPGA features and design, "Clocking", "Clocking wizard 3.6".

Enter a component name, i.e. "myPLL"

100 MHz input frequency is correct, don't change.

Click next.

Page 2: Enter the frequency or frequencies you like (and check the tool output, some frequencies are impossible)

Page 3: Turn off all optional outputs (optional).

Page 6: Check the "...vhdl" filename and click "generate".


This is how I use it:

Locate the generated .vhdl file and copy somewhere else

Remove any files related to "myPLL" that appear in ISE

Move the whole folder away so ISE doesn't find it anymore. If it complains about missing files, click "remove from project".

Add "myPLL.vhdl" as regular source file to the project. For the record, I'm omitting the generated constraints but I've done it this way and the tool figured out the correct frequency by itself.

Insert a "myPLL" instance. There should be an example how to do this in the generated folder, copy&paste.



I think this sounds more complex than it actually is.


The reason for using two modules in series is (AFAIK) that a single stage can't hit the required frequency with sufficient accuracy. The problem is that the least common multiple of 100 MHz and 106 MHz is 5300 MHz which too high for the PLL.

With two stages I can divide 100 by 50 down to 2 MHz, then multiply by 53 (this only to illustrate the concept. The PLL can't handle 2 MHz either but there are other options).


You can edit the generated file manually. This may be necessary if the generated input buffer causes errors. It's easy to remove from the generated code.

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