SDRAM chip model


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Hello Guys,


I am working on a verilog memory controller and have a question about the actual model of the SDRAM chip, my question comes because the physical chip says that it is a MT48LC4M16A2  from micron (which have 12 pin  address bus width), but after checking on papillio pro's hardware guide there is a schematic that says the memory model is a MT48LC64M4A2 (this one have 13 pin address bus width). Also when downloading the generic UCF file from gadget factory website, there are 13 address pins defined there.


I was wondering for which memory model should I design? On the other hand, if memory is MT48LC4M16A2 what is the 13th  address on the  UCF file mapped to?


Thank you

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the only LC64 reference I found was on the schematic. I suspect that the board supports the bigger chip, and A12 goes to pin 36, which is "NC".

It is quite common that different chip sizes are pin compatible so they can be changed without board redesign (the same works for the FPGA, for example).

I'm just guessing here; maybe someone who knows could comment. I would design for the label of the physical chip. My Papilio Pro board uses the same chip, also MT48LC4M16A2.


On second thought: I would not design a memory controller for any chip, not without a very good reason at least.

If the only problem is that you want to use Verilog: Including a VHDL component is fairly straightforward, ISE can handle that.

For example, I've used the XESS memory controller myself (on a Xula board) which is VHDL. I'd start with Hamster's controller on Papilio Pro.

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That is indeed the reason for connecting A13, so the larger chip can be used as well. But the larger chip is much more expensive so we use the MT48LC4M16A2 for production. But A13 is connected in case anyone wants to use the larger chip.


I think Alvie has the correct SDRAM model somewhere, if you poke around his github you will probably find it...



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  • 4 years later...

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