Xilinx VHDL UART Example


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  • 2 weeks later...
  • 9 months later...

Hey Jack,


Any chance you were able to implement this idea already into DesignLab? I couldn't seem to find it. I was looking for an easy way (drop-in) to communicate with some registers on the FPGA without the ZPUino/other soft processors. Any other suggestions to do this would be useful as well.


In fact, it'd be really cool if there was something like a UART that could talk to the wishbone bus registers directly. Is that possible? That would mean we could reuse all the work that people may put into developing wishbone compatible peripherals but who may not need the power/functionality of the ZPUino.



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Hi guys,


That opencores project Jaxartes posted seems like a perfect fit! 


In the future this means we could generate hardware peripherals for DesignLab library that could be instantiated as either standalone or ZPUino-connected which I think is pretty neat and adds some flexibility and reusability.



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  • 3 weeks later...
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The Uart example is very close to what I'm after for communicating with an external device I have.




However I need an 11 bit frame of data and the example uses a 10 bit frame. Is there anyway the code can be modified to allow for 2 start bits and 8 data bits or 1 start bit and 9 data bits? I always need 1 stop bit regardless.


I'm new to FPGAs and have poked around in the code but need a little direction to get me started. 



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