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>> 16 bit shift register

but then the FIFO would have a fixed delay, right?


Nope - the CLB inputs act as "address" registers to a 16 bit shift register, allowing you to select which of the bits to look at. - have a look at "Using Look-Up Tables as Shift Registers 

(SRL16) in Spartan-3 Generation FPGAs"
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I noticed you use 4 bit read and write pointers for a 16-entry FIFO.  If you use 4-bit read and write pointers to figure out if the FIFO is full (i.e. the FIFO has 16 words stored) then you will get into problem since a 4-bit value can't hold the value 16.  Your solution is to say it's full if the FIFO has 15 words stored (wr_ptr+1 = rd_ptr) so you are basically throwing away one location in the FIFO.


An alternative way is to use 5-bit read and write pointers.  This will allow you to differentiate between empty (wr_ptr = rd_ptr) and full (wr_ptr = rd_ptr + 16).  This will also make the logic for detecting full much simpler.  In your case you need a 4-bit adder and a 4-bit comparator to detect full (= 15 words in the FIFO) while this method only adds a couple of gates - it's either empty of full if bits 3-0 of wr_ptr and rd_ptr are the same (i.e. your empty detection), the added logic is that it's empty if bit 4 of wr_ptr and rd_ptr are the same, and full if bit 4 of wr_ptr and rd_ptr are not the same.


When accessing the memory only bits 3-0 of the read and write pointers are used.





Looking at your code again I just realized it's a 32-entry FIFO, not a 16-entry FIFO (I wrote the post after reading your code a few days earlier and somehow I remembered it as a 16-entry FIFO).  However, the basic idea is still the same, just change "4-bit" to "5-bit" and "5-bit" to "6-bit" etc.

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