Problems with using separate modules(noob)


Recommended Posts

Hey there. I'm following this tutorial:

http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/intro-to-spartan-fpga-ebook-r34

 

(By the way there is no code in the repository, only the book itself);

I'm currently on chapter 13 and I'm having problems with getting it to work. I'm supposed to:

 

• Create a new module - a 30-bit counter called "counter30", with the following external signals:
– clk : in STD_LOGIC
– enable : in STD_LOGIC
– count : out STD_LOGIC_VECTOR(29 downto 0)
 
• View the ’Instantiation Template’ for your component. Copy the component declaration into your switches_leds.vhd source
• In switches_leds create an instance of counter30
– Connect the counter’s count output to a bus called count1
– Connect the "enable" signal to switch(0)
– Connect the clock
– Connect the top four bits of count1 to LEDs(3 downto 0).
 
I've spent a ton of time trying to figure out whats wrong but I have no idea. This is what I have so far:
The counter30 module:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter30 is    Port ( clk : in  STD_LOGIC;           enable : in  STD_LOGIC;           count : out  STD_LOGIC_VECTOR (29 downto 0));end counter30;architecture Behavioral of counter30 is	signal counter : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');begin	clk_proc: process(clk)	begin		if enable = '1' then			if rising_edge(clk) then				counter <= counter + 1;			end if;	end if;	end process;end Behavioral;

The main program:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity Swiches_LEDs is    Port (		switches : in STD_LOGIC_VECTOR(7 downto 0);		LEDs : out  STD_LOGIC_VECTOR(3 downto 0);		clk1 : in STD_LOGIC);end Swiches_LEDs;architecture Behavioral of Swiches_LEDs is	COMPONENT counter30	PORT(		clk : IN std_logic;		enable : IN std_logic;          		count : OUT std_logic_vector(29 downto 0)		);	END COMPONENT;		signal count1 : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');begin	Inst_counter30: counter30 PORT MAP(		clk => clk1,		enable => switches(0),		count => count1	);	LEDs(3 downto 0) <= count1(29 downto 26);end Behavioral;

Does anybody know whats wrong?

 

Link to comment
Share on other sites

>> I've spent a ton of time trying to figure out whats wrong but I have no idea.

 

In the great song of FPGA, this is the chorus line :)

 

What usually happens is that the design tool quietly proves to itself that your (buggy) design reduces to a constant. Then optimizes away everything. Try to debug that...

Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.