skp Posted September 20, 2014 Report Share Posted September 20, 2014 Hi There I had purchased a Papilio Pro a while ago, but didn't get time to play around with it. But recently when I tried to program it with the Quick Start bit file, the programmer couldn't recognize it. Suspecting that the FDTI EEPROM might have corrupted or similar, I switched from Ubuntu to Windows and used the FTDIProg utility to read. It looked non-empty, so I erased it and programmed which I thought is the default configuration. It still didn't help To investigate further, I programmed the FDTI with opto isolators activated and soldered in the JTAG pins. However the impact was unable to recognize the device. Not sure whats going on. Any help will be appreciated. The following is the diagnostic outputs from the programmer : xx:~ (master)> pap-check-status Executing /opt/GadgetFactory/papilio-loader/bin//opt/GadgetFactory/papilio-loader/bin/pap-check-status.... Using built-in device listInvalid chain position 0, position must be less than 0 (but not less than 0). ############################################# Programmer status ############################################ Using built-in device listInvalid chain position 0, position must be less than 0 (but not less than 0). Response incompatible with mask xxxx01ISC_Done = 0ISC_Enabled = 0House Cleaning = 0DONE = 0 ############################################# FPGA Status ############################################ Using built-in device listInvalid chain position 0, position must be less than 0 (but not less than 0). STAT RegisterID_ERROR = 0 IDCODE not validated.DONE = 0 Input from the DONE pin.INIT = 0 Input from the INIT pin.MODE = 000b Input from the MODE pins (M2:M0).GHIGH_B = 0 0 = asserted.GWE = 0 0 = all FFs and Block RAMs are write-disabled.GTS_CFG = 0 0 = all I/Os are 3-stated.IN_ERROR = 0 Legacy input error.DCI_MATCH = 0 DCI is matched.DCM_LOCK = 0 DCMs are locked.CRC_ERROR = 0 CRC error.cycleTCK in TEST_LOGIC_RESET ====================================================================================================================================== With exactly the same setup my Papilio500 works without any problem.The diagnostics produces the following output: 2004 pilakkat@pilakkat-W500:~ (master)> pap-check-status Executing /opt/GadgetFactory/papilio-loader/bin//opt/GadgetFactory/papilio-loader/bin/pap-check-status.... Using built-in device listJTAG chainpos: 0 Device IDCODE = 0x41c22093 Desc: XC3S500E ############################################# Programmer status ############################################ Using built-in device listJTAG chainpos: 0 Device IDCODE = 0x41c22093 Desc: XC3S500E ISC_Done = 1ISC_Enabled = 0House Cleaning = 1DONE = 1 ############################################# FPGA Status ############################################ Using built-in device listJTAG chainpos: 0 Device IDCODE = 0x41c22093 Desc: XC3S500E STAT RegisterID_ERROR = 0 IDCODE not validated.DONE = 1 Input from the DONE pin.INIT = 1 Input from the INIT pin.MODE = 001b Input from the MODE pins (M2:M0).GHIGH_B = 1 0 = asserted.GWE = 1 0 = all FFs and Block RAMs are write-disabled.GTS_CFG = 1 0 = all I/Os are 3-stated.IN_ERROR = 0 Legacy input error.DCI_MATCH = 1 DCI is matched.DCM_LOCK = 1 DCMs are locked.CRC_ERROR = 0 CRC error. More over I am able to connect the XILINX Platform Cable II and use it with impact!!! Regardsskp Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted September 22, 2014 Report Share Posted September 22, 2014 Hello skp, The error message, "Invalid chain position 0, position must be less than 0 (but not less than 0)." usually means that there is a problem with the connection between the USB chip and the JTAG port of the FPGA. This is the error message I would expect you to get if you programmed the EEPROM for opto-isolate mode which puts all of the JTAG pins into a High-Z state. It is useful to do this in order to use an external JTAG programmer as shown in this tutorial. But while you are in that mode you will get the above error message. When we ship the Papilio Pro the default is that we actually leave the EEPROM completely empty, so your best bet for getting back to the default is to erase the EEPROM chip. If you erase the EEPROM and then power cycle and still have problems then something might be wrong... Please give that a try and then lets see where we are. Thanks,Jack. Quote Link to comment Share on other sites More sharing options...
skp Posted October 2, 2014 Author Report Share Posted October 2, 2014 Hi Jack Went over it again, but without much joy The drivers etc. seems to be O.K. as I can use FTProg and also with serial term connected to COM9, I can see the led on the board blinking as I type. To make sure FDTI device is blank, I did a "scan & Parse" and got the all "FF" pattern. So I presume, the programming of FDTI is not the problem! Still when I tried loading the Quickstart-Papilio_Pro_LX9-v1.5:1. When I tried to erase and write SPI, it gives the "Invalid chain position 0" message.2. When I tried to write to FPGA, the command did not return!!! Running out of ideas here Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted October 3, 2014 Report Share Posted October 3, 2014 Hey SKP, Given that you setup works with another Papilio board and not this one maybe it is time to trade out your board for a new one. If you shoot us an email at support@gadgetfactory.net with your current shipping address and a link to this post then we can get your board swapped out. Jack. Quote Link to comment Share on other sites More sharing options...
skp Posted December 29, 2014 Author Report Share Posted December 29, 2014 Jack Highly appreciate the kind gesture of quickly replacing the suspect Papilio Pro. Hopefully you received the "faulty" unit.Could only check the new unit during X'mas holidays. Couple of problems/unexpected behaviours: 1) Initially, was perplexed that I could not program even the Quickstart bit files with loader v2.6. Gave Flash verify errors! After quiet some trial & error, noticed that the SPI programming succeeds only if "High Current I/O's" option is checked in the FT_Prog!And erasing the EEPROM leaves this unchecked!If SPI is already programmed with the bit file, it boots and works correctly.But attempting to program the SPI fails with Flash verify error. 2) With opto-isolator on, the SPI programming still succeeds, as lon as #1 is taken care of! How ever turning on any/or both the opto-isolators on seems to interfere with the UART!? [Was expecting leaving opto on on Port A and off on port B to work. And would have given the right combination I was lookng for; Program though SPI or JTAG, debug through JTAG and use the UART ] Would appreciate any help in resolving #2 as I need to use ISE tools (Chipscope) extensively. Regardsskp Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted December 29, 2014 Report Share Posted December 29, 2014 Hello, 1) This is weird that two boards have had a problem, maybe it is related to your system? Can you try with another computer/usb cable/usb port? 2) I don't remember doing extensive testing but I would expect that you put port A into opto-isolate mode and leave port B as it is so UART works as usual. Does this guide help?http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/xilinx-programming-cable-with-papilio-r39 Jack. Quote Link to comment Share on other sites More sharing options...
skp Posted December 31, 2014 Author Report Share Posted December 31, 2014 Hi Jack Yes it is weird. More so, as my Papilio 500K works as expected on exactly the same set up. Had done all those suggested before posting! Infact:1. Started on Ubuntu 14.04 64 bit laptop. Tested with different cables. Also with a powered USB hub2. Switched to Windows 7 32 bit boot on same laptop. Same result.3. Repeated a Windows 7 64 bit desktop where everything was setup from scratch. Same result! While testing on this, just on a hunch enabled the "High Current I/O's". With this it was possible to program and verify the SPI flash with out error. Also the programmed bit file did work as well.4. Tested on the original Ubuntu Laptop. Was able to program SPI flash successfully! 5. Tried to opto isolate Channel A. Oops! UART on Channel B stopped.6. Switched the Channel A opto-isolator off, with no other change. UART works again !? Doesn't seems to be a out right failure like the previous one. Just that can't isolate JTAG to use chipscope.Will do some more investigation when I get time. Regardsskp Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted January 1, 2015 Report Share Posted January 1, 2015 Well, the Papilio DUO shows up as a Xilinx supported cable so you won't need an external programming cable. Maybe we can give you a trade up deal when we get the DUO in stock. Jack. Quote Link to comment Share on other sites More sharing options...
skp Posted January 8, 2015 Author Report Share Posted January 8, 2015 Hi Jack Thanks for your, as usual, generous offer. I may go for it, as I love the look of DUO But I got the setup working as I need, but without a logical explanation. I took a risk and soldered in the JTAG pin and connected to the Parallel Cable. Impact was able to detect AND was able to do the ID Loop test successfully, even though the EEPROM was erased !*#+ ?. I could download bit files through either JTAG or using papilio-programmer and the console port works without an issue! The moment I program the opto on the console stops working! Leaves me totally perplexed. Regardsskp Quote Link to comment Share on other sites More sharing options...
Jack Gassett Posted January 9, 2015 Report Share Posted January 9, 2015 Glad you got it working. Jack. Quote Link to comment Share on other sites More sharing options...
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