Clock generation on the Papilio Pro


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Hi Forum,


I am trying to generate a 128 MHz clock on the Papilio Pro using the stock external 32 MHz oscillator.


I have it setup using the clock management wizard, but can't seem to access the clock signal. How do I tell the IDE that I want to access that generated clock like I could with the clk signal in hamster's tutorial?


For reference, I have attached the code generated by the wizard and my "application" VHDL module - which is similar to the counter example in hamster's book.


Any suggestions will be appreciated!





.v file:


`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "DCM32to128,clk_wiz_v3_6,{component_name=DCM32to128,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module DCM32to128
 (// Clock in ports
  input         P94,
  // Clock out ports
  output        CLK_OUT1,
  // Status and control signals
  input         RESET,
  output        LOCKED

  // Input buffering
  IBUFG clkin1_buf
   (.O (clkin1),
    .I (P94));

  // Clocking primitive
  // Instantiation of the PLL primitive
  //    * Unused inputs are tied off
  //    * Unused outputs are labeled unused
  wire [15:0] do_unused;
  wire        drdy_unused;
  wire        clkfbout;
  wire        clkfbout_buf;
  wire        clkout1_unused;
  wire        clkout2_unused;
  wire        clkout3_unused;
  wire        clkout4_unused;
  wire        clkout5_unused;

  #(.BANDWIDTH              ("OPTIMIZED"),
    .CLK_FEEDBACK           ("CLKFBOUT"),
    .DIVCLK_DIVIDE          (1),
    .CLKFBOUT_MULT          (29),
    .CLKFBOUT_PHASE         (0.000),
    .CLKOUT0_DIVIDE         (7),
    .CLKOUT0_PHASE          (0.000),
    .CLKOUT0_DUTY_CYCLE     (0.500),
    .CLKIN_PERIOD           (31.250),
    .REF_JITTER             (0.010))
    // Output clocks
   (.CLKFBOUT              (clkfbout),
    .CLKOUT0               (clkout0),
    .CLKOUT1               (clkout1_unused),
    .CLKOUT2               (clkout2_unused),
    .CLKOUT3               (clkout3_unused),
    .CLKOUT4               (clkout4_unused),
    .CLKOUT5               (clkout5_unused),
    // Status and control signals
    .LOCKED                (LOCKED),
    .RST                   (RESET),
     // Input clock control
    .CLKFBIN               (clkfbout_buf),
    .CLKIN                 (clkin1));

  // Output buffering
  BUFG clkf_buf
   (.O (clkfbout_buf),
    .I (clkfbout));

  BUFG clkout1_buf
   (.O   (CLK_OUT1),
    .I   (clkout0));





.veo file

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

  DCM32to128 instance_name
   (// Clock in ports
    .P94(P94),      // IN
    // Clock out ports
    .CLK_OUT1(CLK_OUT1),     // OUT
    // Status and control signals
    .LOCKED(LOCKED));      // OUT
// INST_TAG_END ------ End INSTANTIATION Template ---------


.VHDL module

library IEEE;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LED_Board is
    Port ( LED_0 : out  STD_LOGIC;
           LED_1 : out  STD_LOGIC;
           LED_2 : out  STD_LOGIC;
           LED_3 : out  STD_LOGIC;
           LED_4 : out  STD_LOGIC;
           LED_5 : out  STD_LOGIC;
           LED_6 : out  STD_LOGIC;
           LED_7 : out  STD_LOGIC;
           LED_8 : out  STD_LOGIC;
           LED_9 : out  STD_LOGIC;
           LED_10 : out  STD_LOGIC;
              switch_0 : in STD_LOGIC;
              switch_1 : in STD_LOGIC;
              clk : in STD_LOGIC;
              clk128 : in STD_LOGIC);
end LED_Board;

architecture Behavioral of LED_Board is

signal counter : STD_LOGIC_VECTOR(30 downto 0) := (others => '0');


clk_proc: process(CLK_OUT1, switch_0)
if rising_edge(CLK_OUT1) then
counter <= counter+1;
end if;
if switch_0 = '1' then
counter <= "0000000000000000000000000000000";
end if;
end process;

LED_0 <= counter(20);
LED_1 <= counter(21);
LED_2 <= counter(22);
LED_3 <= counter(23);
LED_4 <= counter(24);
LED_5 <= counter(25);
LED_6 <= counter(26);
LED_7 <= counter(27);
LED_8 <= counter(28);
LED_9 <= counter(29);
LED_10 <= counter(30);

end Behavioral;

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the usual way would be to instantiate that component in a Verilog or VHDL schematic.

It works just like any other module you define.


For some strange reason, the input is called "P94". So you'd connect the "P94" port to the oscillator input (which is mapped in the *.ucf file to the FPGA pin that goes to the crystal oscillator).

The output appears then at the CLK_OUT1 output of the component, where you can connect your design.

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Hi offroad,


Thanks for your reply, it helped me to figure out what my problem was! I was trying to instantiate the scheme and the reason I couldn't do it was because I had Verilog output and not VHDL.


This can be fixed by selecting "Preferred Language" as VHDL in the design properties of the project in ISE project navigator.


Once the code generated by the wizard was VHDL code, the instantiation is simple copy & paste.


Thanks a lot for the help!



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