Propeller 1 open source


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I've done a little bit of preliminary work to get the design to run on the Xilinx Spartan as opposed to the Altera Cyclone on the DE0 and DE1.  A couple of tweaks need to be made to account for the differences between the Altera and Xilinx tools (a couple of definitions need to be moved to before they are initially referenced, and the includes needed to be whacked).


The design, as it stands, will not fit on a Spartan 6 LX9. However, it fits on an LX25, which means it would work on a pipstrello just fine, since it uses an LX45.


It occurs to me that if we can modify the design to use fewer than 8 cores, it would fit into an LX9, but there would have to be a lot of testing done to make sure that nothing subtle got borked.


As of right now, I've only gotten the verilog to build and to get a preliminary place and route done.  I haven't done a proper job of setting up pin constraints, which also means that I don't even know if the code will run yet, but at least it builds and routes.

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So it needs atleast an LX25?, on the de0, they said that one need to remove some of the character rom, to be able to make it fit, removing core's might defeat the purpose somewhat?


Would be interresting to see what performance one could get on the pipistrello.. 


So the de0 is infact bigger than the spartan after all?, hm.. 

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I had the same thought about the Cyclone on the DE0 being bigger, but it occurs to me that it's not really an apples-to-apples comparison.  But at least in one aspect, it is.  Mind you, I am using the code that was meant for the DE1 (the difference is exactly as you say).


Also -- I haven't done the work to load the ROM code, so I could be pretty far off of the mark.  This is all just an evening's work, and most of that time was spent waiting for the Place and Route step to complete.


I'm not sure that the LX25 is a minimum. I have a couple of LX9's (Papilio Pro and the Logi-Pi), an LX25 (the XuLa2), and an LX45 (the Pipistrello), so those are the chips I targeted.  I suppose I could be thorough and try other sizes, but the smaller chips take so much time to route...

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While removing the cores may be defeating the purpose of getting the full propeller code running on the chip, I think the coolest part of getting the code is our ability to make it do whatever we want it to do, within our own (meager) abilities.


I'm also enjoying trying to understand the verilog source.


I think the challenge to get arbitrary numbers of cores to work is an interesting one.


But step one is getting the actual original code running, and verified. Once I can run a SPIN program on my FPGA, I'll be happy.

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