gpl gpu in verilog?


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Holy Cow! I need to take a closer look at this, it might be really nice to add it to the Papilio Schematic Library. The amount of memory needed is the biggest hurdle I'm sure, going to read the doc now. Definitely bookmarking for later to keep in the bag of tricks. Thank you for posting this. :)


Anyone care to try to implement it with ZPUino or something?

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Somehow I have my doubts that this will be attractive for a small FPGA.

Too many "*" :

On an ASIC, 8x9 multiplication would be no big deal.


>> PS sadly enough it's in verilog, the "perl" of HDL! :-)

sorry to break the news but that's how your cell phone looks from the inside.

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