papipro Posted July 18, 2014 Report Share Posted July 18, 2014 While trying to test Hamster's high speed frequency counter at 950MHz, a "WARNING:Par:468 - Your design did not meet timing" is generated. Per instruction on http://hamsterworks.co.nz/mediawiki/index.php/High_Speed_Frequency_Counter, I added NET test_signal_p LOC = "P51" | IOSTANDARD = LVDS_33 | PERIOD=1.051ns;NET test_signal_n LOC = "P50" | IOSTANDARD = LVDS_33;NET "prescaled" PERIOD=2.102; to fast_freq_counter.ucf, and modified fast_freq_counter.vhd as followed entity fast_freq_counter is Port ( clk32 : in STD_LOGIC; test_signal_p : in STD_LOGIC; test_signal_n : in STD_LOGIC; prescaled : buffer STD_LOGIC; tx : out STD_LOGIC);end fast_freq_counter; ... process(test_signal) begin if rising_edge(test_signal) then prescaled <= not prescaled; end if; end process; ... i_input_counter: input_counter PORT MAP( test_signal => prescaled, gray_count => gray_count ); According to Design Summary, best case achievable for constraint "NET "test_signal" PERIOD = 1.051 ns HIGH 50%;" is 1.710ns. All other constraints are met. (Unmodified, the original 500MHz vhdl has best case achievable timing of 1.636ns. So the modifications I made make implementation slower.) I seek guidance on solving Par:468 timing error. Thank you for your time. Link to comment Share on other sites More sharing options...
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