Hidden clock in the Spartan 6?

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Did you know that the Spartan 6 has an internal RC Osc running at about 50MHz?


Neither did I. It isn't really documented anywhere. However, here is how to get at it:

STARTUP_SPARTAN6_inst : STARTUP_SPARTAN6   port map (      CFGCLK    => open,         -- 1-bit output: Configuration logic main clock output.      CFGMCLK   => test_signal,  -- 1-bit output: Configuration internal oscillator clock output.      EOS       => open,         -- 1-bit output: Active high output signal indicates the End Of Configuration.      CLK       => '0',          -- 1-bit input: User startup-clock input      GSR       => '0',          -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)      GTS       => '0',          -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)      KEYCLEARB => '0'           -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)   );
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More info in UG380:


In Master configuration modes, the Spartan-6 device drives CCLK from an internal oscillator by default or optional external master clock source GCLK0/USERCCLK. To select the desired frequency, the BitGen -g ConfigRate option is used for the internal oscillator. The default is 2 MHz. The CCLK output frequency varies with process, voltage, and temperature. The data sheet FMCCKTOL specification defines the frequency tolerance. A frequency tolerance of ± 50% means that a ConfigRate setting of 10 could generate a CCLK rate of between 5 MHz and 15 MHz.


Regardless of what option the user selects, the configuration clock in Master mode initially starts at 1 MHz. As the FPGA clocks in the bitstream, it reads in the configuration rate setting and then changes accordingly.

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