Running the SDRAM at about 50MHz (and slower).


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Well, I'm sitting in the work cafe at lunch.... with my Papilio Pro beside me.


The changes needed to work the SDRAM at 50MHz and less are:

In the top_level design:

Change the DCM divisor to hit 50MHz,
          CLKOUT0_DIVIDE => 8,       CLKOUT1_DIVIDE => 8,
          CLKOUT0_DIVIDE => 16,       CLKOUT1_DIVIDE => 16,

In the memory controller

   signal data_ready_delay : std_logic_vector( 4 downto 0);  
   signal data_ready_delay : std_logic_vector( 3 downto 0);  

This causes the data to be latched one cycle earlier.

Little green LED that is the "test past toggle" is now blinking at half the speed it was before

Cool! Enough lunchtime left to go for a cycle!

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