hamster Posted June 16, 2014 Report Share Posted June 16, 2014 I'm thinking about a new version of my frequency counting project, but this time I am thinking something a little more classy for the front end. I'm plaining on feeding the signal under test to be on a clock input, and to be driving a 5-bit Gray counter (either implemented in logic or a RAM block by feeding DOUT into the ADDR), depending on timing. In the project's 'normal' clock domain I will then sample this counter, and use the current and previous value to a look up how many steps the counter has advanced (in a 1024 entry table). These steps can then be accumulated and gated as required. Because it will use Gray coding (where at most only one bit changes at a time) I can drag values back from a high speed domain to the low speed one without any clock domain crossing issues. This should allow signals of up to the max input clock speed to be counted. The main logic can be running at 32MHz or less even less. Anybody see any flaws? Link to comment Share on other sites More sharing options...
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