MiSoC for Papilio Pro

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I've been developing a Python-based SoC framework called MiSoC (successor to Milkymist SoC). Some of its key features are:

  • LatticeMico32 CPU, modified to include an optional MMU (experimental). There is a work-in-progress NetBSD port.
  • Based on Migen, a Python metaprogramming system and toolbox for HDL (think of it as a "generate" statement on steroids).
  • High performance memory controller capable of issuing several SDRAM commands per FPGA cycle.
  • Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI flash controller, Ethernet MAC, and more.
  • High performance: on Spartan-6, 83MHz system clock frequencies, 10+Gbps DDR SDRAM bandwidth, 1080p 32bpp framebuffer, etc.
  • Low resource usage: basic implementation fits easily in Spartan-6 LX9.
  • Portable and easy to customize thanks to Python- and Migen-based architecture.
  • Possibility to design new peripherals using Migen and benefit from automatic CSR maps and logic, automated bus interconnect, etc.

You can find more details here: http://m-labs.hk/gateware.html and get the source from GitHub.


There is now a basic port for Papilio Pro (except the SDRAM PHY - which would be a nice contribution) and for demo/documentation purposes I've made a simple example of a custom MiSoC design: https://github.com/m-labs/blinkie

The code in this repository takes a simple MiSoC base design and adds a core that blinks a LED at a frequency controllable from the CPU via a CSR. The repository also contains example software to control the frequency from the serial console.


I hope you'll find those things useful.




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Hey Sebastien,


Thank you for putting this together for the Papilio Pro. Migen looks really promising, and I had never seen Eda Playground before, very cool!


Taxes are due by April 15th here in the U.S. so I've been fully occupied with getting mine done in time and haven't had a chance to try this out yet. Once I'm done though I'm going to fire it all up on the Papilio and write a Blog post about the experience.


Does Migen use Wishbone? I'd love to look at getting MiSoc included with the Papilio Schematic Library so people could use the schematic editor to draw MiSoc based designs.



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Yes, we do have Wishbone around LM32. MiSoC uses a bus architecture similar to the one from Milkymist SoC, with Wishbone (around the CPU, and for mid-speed DMA peripherals) + a CSR bus (simpler and lower bandwidth) + a high-bandwidth SDRAM bus.

Not sure how Migen/MiSoC would play with the Xilinx schematics editor... I never used the latter.

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