vhdl problem with testbench


sam

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Hi. I'm working on this 32-bit kogge stone adder and I can't seem to get the wavform testbench right. The output signals are giving me H'UUUUUUUU and i cant seem to figure out the solution.
my testbench is as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

COMPONENT ksa
PORT (
A : In std_logic_vector (31 DownTo 0);
B : In std_logic_vector (31 DownTo 0);
Cin : In std_logic;
Cout : Out std_logic;
Sum : Out std_logic_vector (31 DownTo 0)
);
END COMPONENT;

SIGNAL A : std_logic_vector (31 DownTo 0) := "00000000000000000000000000000000";
SIGNAL B : std_logic_vector (31 DownTo 0) := "00000000000000000000000000000000";
SIGNAL Cin : std_logic := '0';
SIGNAL Cout : std_logic := '0';
SIGNAL Sum : std_logic_vector (31 DownTo 0) := "00000000000000000000000000000000";

constant PERIOD : time := 200 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 100 ns;

BEGIN
UUT : ksa
PORT MAP (
A => A,
B => B,
Cin => Cin,
Cout => Cout,
Sum => Sum
);


PROCESS -- clock process for Cin
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
Cin <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
Cin <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;



PROCESS
BEGIN
-- ------------- Current Time: 120ns
WAIT FOR 120 ns;
A <= "00000000000000000000000000000001";
B <= "00000000000000000000000000010011"; 
-- -------------------------------------
-- ------------- Current Time: 160ns
WAIT FOR 40 ns;
A <= "00000000000000000000000000000001";
B <= "00000000000000000000000000010010"; 
-- -------------------------------------
-- ------------- Current Time: 200ns
WAIT FOR 40 ns;
A <= "00000000000000000000000000000001";
B <= "00000000000000000000000000000010";
-- -------------------------------------
-- ------------- Current Time: 240ns
WAIT FOR 40 ns;

A <= "00000000000000000000000000000011";
B <= "00000000000000000000000000000010";

WAIT FOR 520 ns;

END PROCESS;

END testbench_arch;

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I can't quite tell what your problem might be, and I really don't understand what you are doing with the Cin signal as if it were a clock? Unless you are making a Kogge-Stone adder for education purposes, I would suggest just using VHDL's addition operator and let the tool synthesize an adder. I wrote a quick adder and used the Xilinx ISE tool to make a default testbench. It worked as expected. Here is the code and timing diagram. Hope this helps.

Adder:

-- Adderlibrary IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder is   generic (N : integer := 8);   port (      a     : in std_logic_vector(N-1 downto 0);      b     : in std_logic_vector(N-1 downto 0);      cin   : in std_logic;      s     : out std_logic_vector(N-1 downto 0);      cout  : out std_logic   );end adder;architecture rtl of adder is   signal sum : std_logic_vector(N downto 0);begin   sum   <= ("0" & a) + ("0" &  + cin;   s     <= sum(N-1 downto 0);   cout  <= sum(N);end rtl;

Testbench:

-- Adder TestBenchLIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY tb_adder ISEND tb_adder;ARCHITECTURE behavior OF tb_adder IS     -- Component Declaration for the Unit Under Test (UUT)    COMPONENT adder    PORT(         a : IN  std_logic_vector(7 downto 0);         b : IN  std_logic_vector(7 downto 0);         cin : IN  std_logic;         s : OUT  std_logic_vector(7 downto 0);         cout : OUT  std_logic        );    END COMPONENT;   --Inputs   signal a : std_logic_vector(7 downto 0) := (others => '0');   signal b : std_logic_vector(7 downto 0) := (others => '0');   signal cin : std_logic := '0';   --Outputs   signal s : std_logic_vector(7 downto 0);   signal cout : std_logic; BEGIN    -- Instantiate the Unit Under Test (UUT)   uut: adder PORT MAP (          a => a,          b => b,          cin => cin,          s => s,          cout => cout        );   -- Stimulus process   stim_proc: process   begin          wait for 10 ns;         a <= X"01";      b <= X"02";      cin <= '0';      wait for 10 ns;      a <= X"80";      b <= X"7F";      cin <= '0';      wait for 10 ns;      a <= X"F0";      b <= X"0F";      cin <= '1';      wait for 10 ns;      a <= X"FF";      b <= X"FF";      cin <= '0';      wait for 10 ns;      wait;   end process;END;

post-37040-0-36028300-1396568754_thumb.p

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