Modules Help, Please


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I am working my way through the "Introducing the Spartan 3E FPGA and VHDL" from Mike Field, and I've run into a road block.  I'm on Chapter 13, where the ideas of "Modules" is discussed.  I'm in the "Project" section of the chapter and I can't get my VHDL design to compile.  Basically, I am asked to create a 30-bit counter called "counter30" with the following external signals:


  • clk : in STD_LOGIC
  • enable : in STD_LOGIC
  • count : out STD_LOGIC_VECTOR(29 downto 0)

The internal design is up to me, but my earlier counter project could be used to get me started.  I built the "counter30" and it compiles and generates a bit file with no errors.  I viewed the instantiation template and copied the component declaration into another .vhd file called "Chapter10_Clocks," which is my version of "switches_leds" that the book walked me through and then continued through the rest of the instructions.  (I think).


Here is the "counter30" source:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter30 is    Port ( clk 	  : in  STD_LOGIC;           enable : in  STD_LOGIC;           count  : out	STD_LOGIC_VECTOR (29 downto 0));end counter30;architecture Behavioral of counter30 is	signal counter	:  STD_LOGIC_VECTOR(29 downto 0) := (others => '0');begincount <= counter;clk_proc: process(clk, enable, counter)   begin      if rising_edge(clk) then         if enable = '1' then            counter <= counter+1;         end if;      end if;   end process;end Behavioral;

And here is the "Chapter10_Clocks" source:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity Chapter10_Clocks is	Port (		switch  :  in  STD_LOGIC;		LED     :  out STD_LOGIC_VECTOR(3 downto 0);		clk     :  in  STD_LOGIC		);end Chapter10_Clocks;architecture Behavioral of Chapter10_Clocks is	COMPONENT counter30	PORT(		clk 	:  IN 	std_logic;		enable 	:  IN 	std_logic;          		count 	:  OUT 	std_logic_vector(29 downto 0)		);	END COMPONENT;	signal count1	:  STD_LOGIC_VECTOR(29 downto 0)  :=  (others => '0');	beginInst_counter30: counter30 PORT MAP(		clk 	=>   clk,		enable 	=>   switch,		count 	=>   count1	);LED  <=  count1(29 downto 26);end Behavioral;

Here are my constraints:

NET switch  LOC = "P121"  |  IOSTANDARD = LVTTL;  #LogicStart Switch 0NET LED(0)  LOC = "P134"  |  IOSTANDARD = LVTTL;  #LogicStart LED 0NET LED(1)  LOC = "P133"  |  IOSTANDARD = LVTTL;  #LogicStart LED 1NET LED(2)  LOC = "P132"  |  IOSTANDARD = LVTTL;  #LogicStart LED 2NET LED(3)  LOC = "P131"  |  IOSTANDARD = LVTTL;  #LogicStart LED 3NET "clk"   LOC = "P94"   |  IOSTANDARD = LVCMOS25;

And finally, the error I am getting:

ERROR:NgdBuild:604 - logical block 'Inst_counter30' with type 'counter30' could   not be resolved. A pin name misspelling can cause this, a missing edif or ngc   file, case mismatch between the block name and the edif or ngc file name, or   the misspelling of a type name. Symbol 'counter30' is not supported in target   'spartan6'.

Any help that you could offer would be very helpful.  I would rather not move on until I get this fixed and understand what I did wrong.  Thanks again!

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