LogicStart MegaWing

[david1234]

Hi there,

I have downloaded my bit design file to the LogicStart MegaWing as per the book IntroToSpartanFPGABook.pdf.

The design is very simple, it is the one in page 15, and since I am using the papilio pro, I am using the following 

definitions for the ports for led_0,led_1 and switch_0 and switch_1:

NET switch_1 LOC = "P115" | IOSTANDARD=LVTTL;

NET switch_0 LOC = "P114" | IOSTANDARD=LVTTL;

NET LED_1 LOC = "P124" | IOSTANDARD=LVTTL;

NET LED_0 LOC = "P123" | IOSTANDARD=LVTTL;

 

I have also successfully added the "Hello World" bit file which works fine on the papilio pro but the bit file that I have generated does not seem to be working with LogicStart MegaWing.

 

After I download the bitfile I get the following:

JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9

Created from NCD file: Switches_LEDs.ncd;UserID=0xFFFFFFFF

Target device: 6slx9tqg144

Created: 2014/03/14 23:29:14

Bitstream length: 2724832 bits

 

Uploading "X:\fpga_workspace\test\switches_leds.bit". DNA is 0x398581f20cf18efe

Done.

Using devlist.txt

Programming time 765.0 ms

USB transactions: Write 175 read 7 retries 0

 

I also see, the first 3 character displays enabled; is this normal?

Can anyone help?

Thanks,

David

 

switches_leds.bit

[david1234]

Please disregard. After I added the constraint file, I did not "Rerun All" for option Generate Programming File.

Thanks!

[Jack Gassett]

Glad you got it sorted!

Jack.