How does the SPI Flash auto-configure the FPGA?

[Matt Ownby]

Hi all,

 

I've recently been looking into the possibility of making my own PCB with an FPGA on it so I've been studying how my Papilio One configures the FPGA.  I was expecting to see a little microcontroller on the board to do this task but instead, to my astonishment, the only thing on this board that can configure the FPGA is the SPI Flash itself (and the JTAG interface via the FTDI chip).  This is like black magic to me

 

I briefly skimmed the datasheet for the SPI Flash and it does not appear to have any inherent "auto FPGA configure" setting that I could see

 

So my question is, how does this work?

 

Does the FPGA bootstrap the SPI Flash chip or does the SPI Flash chip bootstrap the FPGA?

[alvieboy]

Take a look at:

 

http://www.xilinx.com/support/documentation/user_guides/ug380.pdf

 

Page 40. This will answer your questions, I think

[Jack Gassett]

The ability to boot directly from a SPI Flash chip is something that is built into the Spartan 3 and 6 chips. You just need to setup the M0-M2 pins for the type of SPI Flash chip you use.

 

What is a little trickier though is how do you load a bit file to the SPI Flash? In the case of the Papilio there is a little bit of black magic, we do the following:

 

• There is a special bit file that gets loaded to the Papilio that connects the SPI Flash to the JTAG pins through the use of a BSCAN primitive. 
• Once this special bit file is loaded to the FPGA the papilio-prog application takes over and does the following:
  • Puts the FT2232 chip into MPSSE mode
  • The FT2232 chip then puts the Spartan's JTAG TAP controller into USER1 mode which activates the BSCAN primitive and connects the SPI Flash to the JTAG pins.
  • The FT2232 is then directly connected to the SPI Flash chip and can program it with our bit file accordingly.

Its all a part of the papilio-prog executable which is a fork of the xc3seprog project. I can't take any credit for the black magic that happens here, it was all done by the xc3seprog team... If you use any FTDI chip with MPSSE mode then it will work for you too.

 

Jack.

[Matt Ownby]

The ability to boot directly from a SPI Flash chip is something that is built into the Spartan 3 and 6 chips. You just need to setup the M0-M2 pins for the type of SPI Flash chip you use.

 

What is a little trickier though is how do you load a bit file to the SPI Flash? In the case of the Papilio there is a little bit of black magic, we do the following:

 

• There is a special bit file that gets loaded to the Papilio that connects the SPI Flash to the JTAG pins through the use of a BSCAN primitive. 
• Once this special bit file is loaded to the FPGA the papilio-prog application takes over and does the following:
  • Puts the FT2232 chip into MPSSE mode
  • The FT2232 chip then puts the Spartan's JTAG TAP controller into USER1 mode which activates the BSCAN primitive and connects the SPI Flash to the JTAG pins.
  • The FT2232 is then directly connected to the SPI Flash chip and can program it with our bit file accordingly.

Its all a part of the papilio-prog executable which is a fork of the xc3seprog project. I can't take any credit for the black magic that happens here, it was all done by the xc3seprog team... If you use any FTDI chip with MPSSE mode then it will work for you too.

 

Jack.

 

That is really cool.  Since the flash is only connected to the FPGA, I figured that the FPGA had to be temporarily configured to write to the flash instead of read from it.  That's a pretty neat idea to cut down on hardware costs

 

I just read the Spartan 3E datasheet (section about Master SPI) and looked at the Papilio One Eagle schematics and have concluded that it is set up the following way:

 

M[2:0] is 001 (Master SPI mode)

VS[2:0] is 111 (use "fast read 0x0B" command)

HSWAP: 0 (enable pull-up resistors on all I/O pins during configuration)

 

Thanks for helping me learn!