Porting Logic Analyser from One to Pro


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I am attempting to convert the Logic Analyser to work on a Papilio Pro. Attached are my best efforts so far; ISE fails to build at some point with a cryptic error message:

 

Optimizing unit <BRAM6k8bit> ...WARNING:Xst:2677 - Node <Inst_core/Inst_sampler/ready50> of sequential type is unconnected in block <Logic_Sniffer>.INTERNAL_ERROR:Xst:cmain.c:3423:1.29 -  Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.  

Thoughts?

VHDL_Core.zip

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The idea of having ZAP to act as a central IDE to those schematics is *genial*. Well done, sir!

 

I'm having some difficulties in opening the Bench Sump Logic Analyser in ISE though:

 

ERROR: Failed to load symbols for C:\Papilio-Schematic-Library-1.6\examples\Benchy_Sump_LogicAnalyzer\Papilio_Pro.sch no netlist will be generatedERROR: Could not find symbol "Papilio_Wing_Pinout"ERROR: Could not find symbol "Wing_GPIO"ERROR: Could not find symbol "Wishbone_Empty_Slot"ERROR: Could not find symbol "COMM_zpuino_wb_UART"ERROR: Could not find symbol "ZPUino_Papilio_Pro_V1"ERROR: Could not find symbol "BENCHY_sa_SumpBlaze_LogicAnalyzer8"

In the tutorial page you mention a base project, but it seems the information is already out-of-date in the 1.6 schematic library.

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Yes, things are moving so quickly that the documentation is falling behind. I'll get it all updated soon though, right now I'm trying to lay down the groundwork for how everything works.

 

For the problem you are having you need to add the location of the schematic symbol library in ISE. Go to this tutorial and scroll down a little bit until you get to the section that says, "To add the schematic symbol library we need to go to Tools/Symbol Library Manager." Follow that section and you should be good to go. If you have an older version of the Papilio Schematic Library installed then you might need to delete it from your system. ISE is not very good with dealing with libraries so I've had to experiment with different ways of doing things.

 

Oh, I just realized that it is not obvious where the schematic symbol library is now. It should be located in zap/examples/00.Papilio_Schematic_Library/Libraries/Xilinx_Symbol_Library

 

I better update that getting started guide asap.

 

Let me know if there are any other problems.

 

Jack.

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  • 3 months later...

It's based on Verilog Demon 3.07 but with modifications to use serial i/o instead of SPI.

 

See this thread for more info and source code:

http://forum.gadgetfactory.net/index.php?/topic/1720-demon-307-ported-to-p1-250-500/#entry11322

 

The only change I made for Papilio Pro was to remove the advanced triggers since that code is written using primitives only found in Spartan3 and if compiled for Spartan6 LX9 it wont fit.

 

Magnus

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It's based on Verilog Demon 3.07 but with modifications to use serial i/o instead of SPI.

 

See this thread for more info and source code:

http://forum.gadgetfactory.net/index.php?/topic/1720-demon-307-ported-to-p1-250-500/#entry11322

 

The only change I made for Papilio Pro was to remove the advanced triggers since that code is written using primitives only found in Spartan3 and if compiled for Spartan6 LX9 it wont fit.

 

Magnus

Thank you. Checking the other thread...

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  • 1 month later...

Sure.  See attached zip file for the complete XISE project (ISE 14.4). The .ucf file do have pulldowns enabled on the inputs

 

Note that the advanced triggers (aka HP16500 triggers) are commented out in this version in order for it to fit into the Spartan6 LX9.  The code for this is written using a CLB primitive only found in Spartan3 (SRLC16E) and when synthesized for Spartan6 this primitive is replaced with common logic blocks which takes up way more space.

 

Magnus

 

 

Papilio_Pro_OLS.zip

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Great, I'm going to do a diff with the code for the One to learn where the porting attempt is.

 

I had these errors when switching your original code to X6, but was not sure how to handle that:

ERROR:MapLib:30 - LOC constraint P4 on indata<23> is invalid: No such site on   the device. To bypass this error set the environment variable   'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P3 on indata<22> is invalid: No such site on   the device. To bypass this error set the environment variable   'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P91 on indata<16> is invalid: No such site on   the device. To bypass this error set the environment variable   'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P89 on bf_clock is invalid: No such site on the   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P86 on indata<15> is invalid: No such site on   the device. To bypass this error set the environment variable   'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P53 on indata<6> is invalid: No such site on   the device. To bypass this error set the environment variable   'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P18 on indata<0> is invalid: No such site on   the device. To bypass this error set the environment variable   'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P63 on extTriggerOut is invalid: No such site   on the device. To bypass this error set the environment variable   'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P90 on tx is invalid: No such site on the   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P25 on armLEDnn is invalid: No such site on the   device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

Diffing may give me a lead on how you do that. Eager to learn.

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I've rebuild and tested an i2c circuit with and without pulldowns:

 

(tested by altering A0 and A1 as follows):

# indata[0-15] mapped to Wing A[0-15]NET "indata[0]" IOSTANDARD = LVCMOS33;....NET "indata[1]" IOSTANDARD = LVCMOS33;.....

With pulldowns configured for A0 and A1: i2c signals approx 1 volt down

 

NewFile1.bmp

 

 

without pulldowns for A0 and A1: virtualy no impact on signal

 

 

NewFile0.bmp

 

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I have seen this board while troubleshooting my build of the IOBuffer - I have been thinking about going for the NPX/Philips IC for my implementation, but landed with the TI one (and that works fine).

 

Inspired by the Pipistrello wing, I might change the constraint file of the Pro project you loaded here to use the 'C wing' connector for 16-31 too in stead of the 'B wing'.

In my PCB design for the buffer I did not place the wing headers exactly on the board edge, so I can't plug one into 'A' and one into 'B'.

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  • 4 months later...

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