Hugo Sereno Ferreira Posted March 1, 2014 Report Share Posted March 1, 2014 I am attempting to convert the Logic Analyser to work on a Papilio Pro. Attached are my best efforts so far; ISE fails to build at some point with a cryptic error message: Optimizing unit <BRAM6k8bit> ...WARNING:Xst:2677 - Node <Inst_core/Inst_sampler/ready50> of sequential type is unconnected in block <Logic_Sniffer>.INTERNAL_ERROR:Xst:cmain.c:3423:1.29 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. Thoughts?VHDL_Core.zip Link to comment Share on other sites More sharing options...
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