Looking for VHDL Code for Quickstart-Papilio_One_500K-v1.5.bit


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I am working with the Papilio one and the Logicstart wing.


I am trying to follow the e-book "Introducing the Spartan 3E FPGA and VHDL" by Mike Field. I cannot get past the first project (chapter 6). I have modified the constraint file to:


#Constraints for Papilio 1
NET Switch_0 LOC = "P91"  | IOSTANDARD = LVTTL;
NET Switch_1 LOC = "P92"  | IOSTANDARD = LVTTL;
The LEDs do not respond to any of the switches. The LEDs are all off. All the segments of 7-segment display are lit.
Quickstart-Papilio_One_500K-v1.5.bit works as expected. 
I suspect that there could be change in the mapping of the FPGA pins to the LEDs, switches, and 7-segments.
If I could get the source for Quickstart-Papilio_One_500K-v1.5.bit, I could check if there is a problem with the mapping. Where could I get the VHDL source?
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Well, the quickstart bit file is made using the ZPUino soft processor. The source code is not in VHDL, it is a c++ sketch instead.


But here is a collection of ucf files for the Papilio boards that might get you the information you are looking for.


Maybe you can just do something like:


LED_0 <= '1';


That should turn the LED on and verify you have the ucf file right.



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Wecome aboard aaremnair!


Yes, starting out in Logic programming is one frustrating beast sometimes. Just don't get discouraged and give up.

I don't really know enough to fully troubleshoot your problem but here is some things to verify.


Make sure you have the device setting on XC3S500E and the correct package VQ100 (for the 500K board).


The names between your vhdl file and ucf file must match, so it might be a good idea to make your ucf file in all caps since the compiler makes all lowercase 

letters caps when it builds the implementation file (not sure about this but it rules one more thing out).

Also, just use SWITCH(0) the underscore might not work.

I would just change the names you use in VHDL to match the UCF file you already downloaded this way to don't have to write a new ucf for every project.

You can always use # to comment out a line in the ucf, but some are needed almost all the time, like the clock (but the PERIOD=31.25ns can be removed).


The compilers are also picky about needing the top level set to your schematic or VHDL file.

I select the option to allow unlocked LOC constraints otherwise the project will not build unless you use every pin in the ucf. This can hide some problems but it allows you to build a project that doesn't use every pin. Yes, you will get alot of warnings about trimmed locations and such.

Turn the output bit stream on or you won't get a bit file.

Also, check the clock settings if it is set to Jtag in Xilinx the bit file must go to the FPGA not the SPI flash in the papilio programmer as I recently found out.

CClk can go to the SPI flash. Just put your bit file in the right papilio programmer box and select the destination and you should be good to go (don't worry about the empty file box bmm and hex).


There are a ton of settings in Xilinx and if some are not right it won't work at all. If your still stuck post as much info as you can so people can help in a more focused way than this rambling post of mine. Hope something in this post helps you. Sorry, If I covered something you already checked. You seem to have a good idea of what you are doing, so good luck and post any updates on getting it working (like what you had to do) because I have noticed new members have the same problems over and over. So your post could save someone else from having to post the same problem.  

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Thanks to both Jack and MicroN8. Finally I have my first VHDL program executing (using Switch_0 to control LED_0:-)


What worked was the configuration in the file BPM7003-Papilio-One-LogicStart-MegaWing-general_1.2b.ucf. Thanks Jack for the suggestion to look at the bunch of ucf files; also the tip about LED_0 <= '0'.




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