Overview of an SDRAM transfer.


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Just like to share with you guys an overview of a typical block transfer from the SDRAM. This is used by the ZPUino instruction cache and (for version 2) also the DMA channel.


This goes as fast as possible can go. The wishbone data interface witdh is 32-bit, and the SDRAM is 16-bit, so it takes 2 cycles to grab the whole 32-bit word from the SDRAM.




In this image we can see the wishbone starting a cycle (asserting the CYC signal), and strobing an address (by asserting the STB signal). If you look more clearly (you cannot see the whole address value here), right after strobing the first address, the STALL signal from the sdram controller is asserted. At this point, the system already has a new address on the bus, and will hold it there until the STALL signal from the controller goes low again. It then proceeds to the next address. This up to the point that there are no more addresses to place on the bus, where the master lowers the STB signal, but it keeps the CYC signal on.


Right after the first address strobe, the SDRAM starts to receive the requests. They are also bursted, so you see that addresses are changing even before the first reply from the SDRAM (just after the first high-z period, the longer one on the DQ line). Again, we pipeline even at the SDRAM level, not only at the wishbone level.


When the first data starts to come out, you can see the ACK signal from the controller, signaling that data is valid. We keep on getting an ACK each 2 clock cycles until we have read everything we bursted into the SDRAM controller, after which the master lowers the CYC signal, relinquishing the SDRAM for other masters that may exist.


A closer look:




Here you can see the start of the transaction, with the proper values filled in. Notice how the clock and the SDRAM lines are not aligned: this takes all the IO delays into account.



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Heh, sorry Alvie, I was meaning to reply but was unable to come up with anything meaningful. :)


Once I start digging into how SDRAM transfers work I'm going to be, "Ah ha! This is great information.". But right now I'm a bit at a loss...


It would be really, really great if we could come up with a SRAM type interface like you talked about in another thread. Then add it to the schematic library so people can access the SDRAM without all the hassle there is now.



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