Jack Gassett Posted January 6, 2014 Report Share Posted January 6, 2014 Hey everyone! We've learned a lot from the Papilio One and the Papilio Pro, its time to take those lessons and apply them to a next generation Papilio board. I mentioned a new board earlier, similar to the never released Papilio Logic, and many of you privately provided some great feedback. My head is swimming with new ideas and I wanted to take some time to write it all down and ask for feedback, help, and ideas. The goal with this new board is to make it useful and appealing to all electronics enthusiasts, not just those into FPGA's. I want it to be the first thing you pick up when you have an idea you want to try out, the most useful electronics multi-tool on the desk. That's why I'm code naming it - Papilio Benchy - to convey that goal. What we have learned from the Papilio One, Papilio Pro, and Papilio LogicProbably the most often heard request is for the Arduino footprint. People really want to use the vast library of Arduino shields that are out there. I learned with the Papilio Logic that one of the headaches of the Arduino footprint is the analog pins. Using an SPI ADC was a mistake... The next often heard request is to provide lots of external RAM, and SRAM instead of SDRAM. SDRAM is hard to interface while SRAM is a piece of cake. Not fully connecting the SRAM chip severely cripples is usefulness. Connecting BLE and BHE to ground is a mistake... We need high speed USB, the FT2232D is only capable of 3Mb/s the way we have it connected. Lets upgrade to 480Mb/s... It sucks that we can only use one of the two FT2232 channels in our FPGA designs. I often wish I could have one serial channel for sketch output and another for logic analyzer output. Not having a full FT2232 MPSSE channel connected limits what we can do. Connecting to a computer and loading a bit file when you change shields is tedious. Selling a solution such as the RetroCade Synth as a kit that someone has to download all the Papilio software and program a bit file before they can use it is not user friendly. Many people who buy the synth want to use it as a synth, they don't care about the FPGA stuff... Switching power supplies are the way to go, the extra cost is worth it. Putting a Papilio One in a case with those linear regulators isn't going to fly. Eliminate through hole parts, the more through hole soldering is done the dirtier the board is after assembly. HDMI!!!!!!!!!!!!!How to apply those lessons to the Papilio BenchyIf you can't beat 'em, join 'em. The next Papilio board will use the Arduino Mega footprint, pins 30-55 on the right side of the board will be modified to allow Wings to be connected to them. People can plug Arduino Shields in and still add ala carte functionality using the Wing slots on the right instead of stacking shields. MegaWings will be replaced by shields going forward. On the Papilio Logic, which was an Arduino Mega footprint Papilio board I made in 2011 I used an SPI ADC chip to implement the analog pins. This was one of the reasons I never brought this board to market, the price of SPI ADC chips shot up drastically after I finished the design... I also shared the pins with 53-55 on the Arduino footprint which I didn't like. Logxen pointed out a much more elegant solution that kills several birds with one stone. Use an AVR for the analog pins... Well, why stop there, the Atmega32u4 used in the Arduino Leonardo is just about the same price as the SPI ADC that I used. We can add a full blown Arduino to the design for about the same price. If we have the FPGA pins and the Arduino pins both connected to the Arduino footprint then we can run fully compatible Arduino sketches on the Atmega32u4 and use the FPGA as a Logic Analyzer or debugger. We also get all the benefits of the Arduino Leonardo, such as more flexible USB types... This is going to be a routing challenge, but if we need to go to a multi-layer board then it is worth it. All of the SDRAM on the Papilio Pro is nice, but it is hard to use. With the Papilio Benchy we should use SRAM instead. The reasons for using SDRAM over SRAM were: 1) cost 2) fewer pins. After doing more research on the Chinese parts market I was able to determine which SRAM parts are plentiful and cheap. I noticed that there are plenty of 8 bit parts out there for very affordable prices. If we move from the 16 bit part to an 8 bit part then we will free up some critical pins and might be able to squeeze SRAM and a full speed FT2232 MPSSE channel into the design. One such chip is the IS61WV20488, if you look at it on digikey it is scary expensive $14. But a search on Taoboa shows it for around $8. If that is too expensive then we can always fall back to a 512Kx8 chip which is around $4 on digikey and $1.64 on Taoboa. Moving to an 8 bit part should allow us to fully connect it. We will upgrade from an FT2232D to the FT2232H, which is actually a cheaper and more capable chip! It does 2.0 480Mb/s and has two full MPSSE channels. The FT2232D only had one MPSSE channel. I want to connect both channels to the FPGA this time. Channel A will still be connected to JTAG for programming, but the rx and tx pins will also be connected to the FPGA for a low speed, 3Mb/s, serial channel. There are some question marks here, but I suspect that if we keep cts disabled, which is connected to the FPGA JTAG TMS pin, while we use the channel A rx and tx pins it will never activate the JTAG programming on the FPGA. Worst case scenario we need to add some kind of switch to disconnect the TMS pin. Channel B will hopefully be fully connected to the FPGA. Worst case scenario we can only connect the first 4 MPSSE pins and will not be able to achieve full 480Mb/s. The FT2232H, unlike the FT2232D, has MPSSE on both channels! Yeah! I would like to embed some kind of one wire identifier chip on the shields and have all of the Papilio bit files stored in SPI Flash and controlled by multi-boot. When a shield is connected to the Papilio Benchy the golden image will read the identifier chip and multi-boot to the correct bit file. This will take some work but will go a long way toward end user convenience. Imagine connecting a Logic Analyzer shield and the Sump logic analyzer bit file is automatically loaded. Then we can have software that reads the ID when you plug the board into a computer and will automatically start up the Sump Logic Analyzer client. Or how about a shield with a ZIF socket that loads a bit file that connects the MPSSE pins in a way that allows the Flashrom project to work... That will go a long way towards making the Benchy the first tool you would grab when you need something... Not much to say here, upgrading to the power supply used on the Papilio Pro is a no brainer. Not much to say either...Summary of proposed features to implementArduino Mega footprintArduino Leonardo implementation side by side and sharing the pins with the FPGA. There will be two USB connectors for a total of 3 serial channels to the board. The Atmega32u4 will implement the analog pins which the FPGA can read over a SPI channel.8 bit SRAM chipFT2232H with Channel A connected to JTAG and rx/tx connected to FPGA pins. Channel B fully connected if possible, if not then just the 4 MPSSE pins.HDMI portThis is a wishlist, it will be a juggling act to pull all of this off and compromises will undoubtedly have to be made. It is ok to go to a 4 layer board instead of a 2 layer board, but for this board I'd like to avoid BGA. There are other ideas for a high end BGA board... Jack. Link to comment Share on other sites More sharing options...
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