Creating a Clock Output from Papilio


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My second newbie question, hopefully someone can help me and I'll be forever grateful.


I'm using my recently purchased Papilio one 500k to create a 24MHz clock output to feed into a different chip/module.

Why am I doing this? Because I bought the wrong oscillator for my other module and I thought hooking it up on the fpga would a quick temp solution.


The design is super simple, just the regular 32Mhz clk in, to a DCM which modulate to 24Mhz, then to ODDR2 which drives an OBUF on one of the IO pins.


The output pin is set as LVCMOS33 in my ucf and the OBUF driving it is also LVCMOS33 standard.


However, when I measure the output on the board with an oscilloscope, the waveforms are really distorted but correct frequency. As if there's too much parasitic cap on the output. Going down to a much smaller freq around 8Mhz the waveforms are much more square. I've calibrated my probes over and over again.


Are the "wings" or headers on the Papilio bad for driving such signal? Or do I need to change some iostandard or drive strength? Any advice suggestion?



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When you say distorted I assume you mean something like this (sorry, stock photo off google search). This is called ringing and it's due to the very fast rise signals typical of FPGAs'


If so, I'm sort of dealing with the same issue, but just have not had much time for the last week to do a proper post. Even now I'm away from home doing this quick post. If no one else helps you in the meantime, I will try an find some solutions in the next couple of days.

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Hi Camera_boy,


Are you using a DDR output to 'forward' the clock?


You use a DDR register to output '1' during the first half of the clock cycle, and then a '0' during the second. Because it is is using the I/O infrastructure within the FPGA (rather than routing internal signals to the outside world) you will get the best results, and the skew should match that of other output signals


You do it like this:

Library UNISIM;use UNISIM.vcomponents.all;clock_forward : ODDR2   generic map(DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC")   port map (      Q => Q,        -- 1-bit output data      C0 => Clk,     -- 1-bit clock input      C1 => not clk, -- 1-bit clock input      CE => '1',     -- 1-bit clock enable input      D0 => '1',     -- 1-bit data input (associated with C0)      D1 => '0',     -- 1-bit data input (associated with C1)      R => '0',      -- 1-bit reset input      S => 'S'       -- 1-bit set input   );  
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Alex- It's not exactly the ringing effect, its more of a clock degradation, as if there's some large parasitic on the output, or a large RC on the load. Almost seems like the drive output buffer cannot drive the load fast enough. When I lower the frequency, it is much more square. Similar to this (google picture, I can get a shot this weekend) but actually even worse at 24Mhz.



Hamster- I am using ODDR2 to forward the clock, here is my verilog:

ODDR2 #(    .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"     .SRTYPE    ("SYNC") // Specifies "SYNC" or "ASYNC" set/reset) ODDR2_inst (    .Q     (clk_out),   // 1-bit DDR output data    .C0    (dcm_output_clk),   // 1-bit clock input    .C1    (~dcm_output_clk),  // 1-bit clock input    .CE    (1'b1),       // 1-bit clock enable input    .D0    (1'b1),       // 1-bit data input (associated with C0)    .D1    (1'b0),       // 1-bit data input (associated with C1)    .R     (1'b0),       // 1-bit reset input    .S     (1'b0) );     // 1-bit set inputOBUF #(	.DRIVE(12),	.IOSTANDARD("LVCMOS33"),	.SLEW("FAST")) OBUF_inst (	.O(C[9]),	.I(clk_out));	 
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I drive a spi clock of a SDCard at 48Mhz with this constraint in my Papilio One 500k project and a micro sdCard wing:

NET CS                          LOC = "P35"  |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST ; #

Have you try a measure with a disconnected load ?

What is exactly your load ? If you try to clock a micro-controller by this way, you may check the input datasheet of the mcu. Sometime such device require specific fuse setting to work with different oscillator technology.



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This is not terribly surprising to me. 24 MHz is high enough frequency to be considered RF. Look up the capacitive and inductive reactance calculations at 24 MHz and you'll see it doesn't take much stray reactance to have a large effect.


It may not matter though, depending how bad the distortion is. Have you tried driving your project with the signal to see what happens? It isn't uncommon for the waveforms in high frequency digital circuits to be far from perfect clean square waves, and the scope probe will have some effect on them too.

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Thanks for everyone's reply, yes I agree it must be the reactance causing the distortion. I've tried other pins and using TTL as suggested by Tb_ and results were similar. The scope may definitely have some effect too.


I was able to drop the frequency to 16Mhz and my module (an image sensor) was still able to function correctly, so I will leave as is and will substitute with a real oscillator later on.


Thanks for all the feedback.

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What is the bandwidth of the scope you are using?  To see the true waveform of a 24 MHz square wave you will need something like a 500 MHz - 1GHz scope.  If you use a 100 - 200 MHz scope then you loose all the high-frequency components of the waveform.  Just to check, measure the 32MHz clock from the on-board oscillator, if it looks just as bad then you most likely have a scope issue.

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So a quick update, last night I probed the 32Mhz oscillator directly with my scope and the waveform was perfect square at 32MHz, so the problem is not with the scope or probe. I still think it's related to the stray parasitic effect from the board/IO/wing at such frequency or some IO buffer related issue in my design.


If anyone has wants to do a quick experiment to confirm, that would be cool! 

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