clock tiles getting no where


Chris_C

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I've tried the wizard and manual creation but I seem to be getting now where :(

 

I'm obviously missing something "obvious"

 

I can't seem to specify a specific pin in the constrains file

NET CLK LOC = "P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns;

 

gets me

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD=LVTTL |>   [constraints.ucf(4)]: NET "CLK" not found.  Please verify that:   1. The specified design element actually exists in the original design.   2. The specified object is spelled correctly in the constraint source file.ERROR:ConstraintSystem:59 - Constraint <PERIOD=31.25ns;> [constraints.ucf(4)]:   NET "CLK" not found.  Please verify that:   1. The specified design element actually exists in the original design.   2. The specified object is spelled correctly in the constraint source file.

I'm fairly sure the clock input in the generator is specified as automatic single ended

 

its buffered but I can't seem to see any way to connect an external source into any part of this automagically created black box...

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ahhh the penny drops! I simplified the design down to just a clock / counter and LED (what I should have done in the first place)

 

for some reason I assumed that the wizard connected everything up for you....

 

I now see that it makes a component for you only, and you need to instance it for yourself and connect up the the outputs and inputs with your own signals....

 

finally !

 

digital design == easy, vhdl + ISE != easy !!!

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