clock tiles without wizards


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I'm really not a fan of wizards - they tend to hinder understanding and hide stuff from you ...


Is there any generic VHDL way to use the clock tiles to provide a specific frequency, say for the sake of argument 100mhz


if you need some other file type other than VHDL, what? can they be "hand made"

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PLL_BASE_inst : PLL_BASE generic map (      BANDWIDTH      => "OPTIMIZED",        -- "HIGH", "LOW" or "OPTIMIZED"       CLKFBOUT_MULT  => 16 ,                 -      CLKFBOUT_PHASE => 0.0,                      CLKIN_PERIOD   => 20.00,                    CLKOUT0_DIVIDE => 8,       CLKOUT1_DIVIDE => 8,      CLKOUT2_DIVIDE => 1,       CLKOUT3_DIVIDE => 1,      CLKOUT4_DIVIDE => 1,       CLKOUT5_DIVIDE => 1,      CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5,      CLKOUT2_DUTY_CYCLE => 0.5, CLKOUT3_DUTY_CYCLE => 0.5,      CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5,      CLKOUT0_PHASE => 0.0,      CLKOUT1_PHASE => 0.0, -- Capture clock      CLKOUT2_PHASE => 0.0,      CLKOUT3_PHASE => 0.0,      CLKOUT4_PHASE => 0.0,      CLKOUT5_PHASE => 0.0,            CLK_FEEDBACK => "CLKFBOUT",      COMPENSATION => "SYSTEM_SYNCHRONOUS",      DIVCLK_DIVIDE => 1,      REF_JITTER => 0.1,      RESET_ON_LOSS_OF_LOCK => FALSE      CLKFBOUT => CLKFB, -- 1-bit output: PLL_BASE feedback output      -- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs      CLKOUT0 => CLKu,      CLKOUT1 => open,      CLKOUT2 => open,      CLKOUT3 => open,      CLKOUT4 => open,      CLKOUT5 => open,      LOCKED  => open,  -- 1-bit output: PLL_BASE lock status output      CLKFBIN => CLKFB, -- 1-bit input: Feedback clock input      CLKIN   => clkb,  -- 1-bit input: Clock input      RST     => '0'    -- 1-bit input: Reset input   );   -- Buffering of clocksBUFG_1 : BUFG port map (O => clkb,    I => clk_50);BUFG_3 : BUFG port map (O => clk,     I => clku); 

Using clock tiles without wizards is very ugly - I usually use the wizard and then lift the important bits out of the vhdl file in the IP_core directory. Far less chance of errors, far more chance of it working :)

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hey that's great! (we love fugly code!!!)


any reason the buffers are numbered with odd numbers...?


I assume things like (random example) CLKOUT2_DUTY_CYCLE is exactly as named in the datasheet?


while on the subject of clock's soft cores seem limited to 100mhz is this the practical limit for a -2 grade fpga using a moderately complex circuit?

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Yep - you can find examples under Edit/Language Templates for most things, including clocking bits and bobs. The clock buffers are completely random.


The speed that can be achieved is determined by lots of things - I have sent serial data between two Spartan 3E FPGAs at 512Mb/s but is was very, very hard work.


Simple logic (one CLB between registers, limited fan-out on signals) can go at about 220MHz on a Spartan 3E, and maybe 300MHz on a Spartan 6. It all goes down-hill from there as your design's complexity grows.

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