Lstout Posted November 19, 2013 Report Share Posted November 19, 2013 Hi, For some real time reason i would like to give acces to one of my VHDL module to the SDRAM.I manage to do it with the SDRAM wrapper used in the ZPUino. My problem is that on papilio pro board the ZPUIno uses the 8Mb SDRAM ressource to store and run sketches.So i can not manage to share the use of the SDRAM between the core and my vhdl module. I was wondering if it was existing a way to do that ? Or may be if a configuration was existing to setup the ZPUIno to make it use the 64Kb of SRAM avalible on the LX9 chip to run sketches, and let the SDRAM free to be used by a vhdl module ? am i clear ? Link to comment Share on other sites More sharing options...
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