Switching RAM ressources in ZPUIno on Papilio pro


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For some real time reason i would like to give acces to one of my VHDL module to the SDRAM.

I manage to do it with the SDRAM wrapper used in the ZPUino.


My problem is that on papilio pro board the ZPUIno uses the 8Mb SDRAM ressource to store and run sketches.

So i can not manage to share the use of the SDRAM between the core and my vhdl module.


I was wondering if it was existing a way to do that ?


Or may be if a configuration was existing to setup the ZPUIno to make it use the 64Kb of SRAM avalible on the LX9 chip to run sketches, and let the SDRAM free to be used by a vhdl module ?


am i clear ?

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You should try a global variable at a known address in you program.


Take a look at this blog entry : http://mcuoneclipse.com/2012/11/01/defining-variables-at-absolute-addresses-with-gcc/

The basic idea is to associate an gcc attribute to your variable and make reference in your linker script to fix the address.
So at compilation time. The tool will not use the reserved space unless your program does it. It should also be possible to forbid the use of the complete space in the linker script.
But this only prevent your sketch to be strew in all the memory and will not solve how your design have access to the memory data
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We do allow for DMA transfers between one device and memory. For ZPUino 1.X, the interface is a classic Wishbone interface. For ZPUino 2.X (in the works) the interface is Wishbone pipelined, so you can get more data per transfer.


All transfers are 32-bit.


For one example of this, you can see the ZX Spectrum VGA interface (1.X):




For 2.X version, I can get you the HDMI VGA adaptor, which uses pipelined interface for a 640x480 display.

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