New To The Community - Wonder If This Is A Problem

[Wile_E_Coyote]

Hi, all.  New to the community and new to FPGAs. I am an EE by trade, and wanted to get some exposure to working with FPGAs for fun, and to open opportunities in SOC design and such.

 

I was going through the tutorial on pipilio.cc website, and I got some anomalies (I think).  The code seems to be working correctly, but the ISE is reporting possible issues.  Here's what I get when I compile:

 

 

There are multiple pins listed in the warnings, so this is just a short list of them.

 

 

Here is where it shows a warning in the Process window.

 

 

Finally, I looked in the UCF to see if I could correlate the pins that were listed in the warning were common to something (anything), and it appears that they are related to the SDRAM addresses.

 

So, is this a problem? I don't like seeing the '!' in the triangles.

 

Thanks!

[hamster]

Hi,

 

You usually can't get rid of the warning triangles - unlike in SW development any complex design will cause some warnings - for example a single bit on a bus might always be zero. On any working project all of the warnings can be ignored. On a misbehaving one they usually hint at why something isn't quite right.

 

There are two options here - both of them suck a little:

 

1. If you turn on the "allow unmatched LOC constraints" setting for the "Implement Design".step of the build (right click on it and choose "Properties") you get warnings, (instead of errors) if you don't use all the signals defined in the UCF file.

 

2. Delete or comment out the unused signals in the UCF file, you can then disable this setting.

 

I prefer option 2, as all the warnings go away. Others prefer option 1 as you don't have to keep editing the UCF file.

 

Mike

[Wile_E_Coyote]

I see...I did option 1 all ready and was sort of disappointed that I still got warnings, which prompted this post. I'll try option 2 this time; however, if it really doesn't matter, maybe it won't matter.

 

Thanks!

[Jack Gassett]

Thanks for joining us! This is the one constant complaint that always comes up. Every time I attend some training event at Xilinx there always seems to be someone who brings it up, so it is something that everyone feels and Xilinx is aware of. There are just tons of warning that occur in any but the most trivial of designs, you have to learn what to pay attention to and what to ignore. Like hamster I usually ignore warnings unless something is not working as expected, then I dig into the warning to figure out which one could be the culprit. Xilinx is working to address the problem, their solution is Vivado design suite... Unfortunately they are only supporting new series 7 chips with Vivado at the moment.

 

Jack.

[james1095]

One of my biggest gripes about ISE is that the error and warning messages are next to useless. Many times an error in the code will cause a cryptic error that does not appear to have any relation to the problem that triggered it.

 

In this case you might try creating a new constraints file from scratch and locate it in the folder with the rest of the files for your design.