Wile_E_Coyote Posted November 9, 2013 Report Share Posted November 9, 2013 Hi, all. New to the community and new to FPGAs. I am an EE by trade, and wanted to get some exposure to working with FPGAs for fun, and to open opportunities in SOC design and such. I was going through the tutorial on pipilio.cc website, and I got some anomalies (I think). The code seems to be working correctly, but the ISE is reporting possible issues. Here's what I get when I compile: There are multiple pins listed in the warnings, so this is just a short list of them. Here is where it shows a warning in the Process window. Finally, I looked in the UCF to see if I could correlate the pins that were listed in the warning were common to something (anything), and it appears that they are related to the SDRAM addresses. So, is this a problem? I don't like seeing the '!' in the triangles. Thanks! Link to comment Share on other sites More sharing options...
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