Mojo buyer - regretted :(


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First of all, I'm sorry for asking my question here, I don't have a Papilio, instead I've bought a Mojo v3, and I think I will regret it for a long time... The hardware is fine, it's the support forum that bugs me, almost dead :|

Also, I'm still a newbie on FPGA so here it goes:

Mojo communicates with the AVR onboard and then with the PC via serial port (
I've been using this project as starting point, and want to make a simple change:
Input data via serial, and after pressing Enter, the FPGA would return the data again.
I think I need a shift register and ram right? or just a big vector?
Could someone point me some tutorial or best way to acomplish this?
I can only use 8bits with tx_data and rx_data.
After understanding this, what I really want is to send a string, have it processed by a MD5 core, and then make it return the hash, everything via UART.


BTW: After I understand the basics, my intention is to convert this:

To Spartan6LX9, without VGA or PS2 keyboard. Yep, still a loooong way, too much to learn :)

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I am very unhappy to hear that you purchased a Mojo :) As I am sure you are aware, if you were using a Papilio, then you wouldn't have the AVR in the loop, and you would have a lot more willing helpers.


However, if you dig around on my Wiki ( you might find projects of interest.


But in answer to your question you need to receive the data, move it into the format you need for processing - whatever matches your cores requirements - then transmit the data back to the host once processed. 


Transmitting is easy, receiving is harder. All of this is covered

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Hi hamster.

Love your tutorials/projects! You're refered all over the web on FPGA related pages and foruns :) And yes, already had those links :)

As stated above, I'm still a newbie with Verilog, however, communication with PC is fine, I can work with it as long as I send/receive 8bits.

My problem is, where to store it?

Should I create a RAM core via the IP generator?

A pratical example:

I send 8 chars, being 8*8, where do I keep these 64bits, so that I can transmit them back to the PC ???

If you check the HelloWorld example, you'll see that they already provided the UART part, so this is no big deal.

Thanks again.

PS: The Mojo hardware is nice, and the tutorials too, don't get me wrong, I just dislike the lack of support via the official forum.

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Hello yabapolido,


Whether you are using a Mojo or the Papilio I'm happy that you are getting involved with FPGA's. :) I'm biased towards the Papilio because it is my design and I'm supporting my family solely from Papilio sales. :) But either way the goal is to bring FPGA's into the mainstream and make tools, tutorials, and communities to help bring that goal to life.


So you have three options, that I know of, to store your 8 bytes of data:

  • Block RAM
  • Distributed RAM
  • Use Registers in the FPGA fabric

You can use the IP generator to make BRAM or DRAM, but I think BRAM is overkill. The smallest BRAM block is 9Kbytes, much more then the 8 bytes you need. I've never personally used the Distributed RAM, it might be a good fit here but I think using registers is the best approach here.


Unfortunately I don't deal with Verilog enough to give you an example, but you can see how to setup a single bit register if you look at the language templates in the ISE editor. Open Language Templates and go to Verilog/Synthesis Constructs/Coding Examples/Flip Flops/D Flip Flop/Posedge/Simple Register. You will just want to expand that to 64 bits, the key thing here is that you want to use a register to store the data for later use.


It might also help to search for "register verilog example" on google. Or maybe someone who uses verilog can give a more concrete example.



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See attached zip file with a complete ISE project that does what I think you are looking for.  It buffers up to 2047 bytes in a ram and sends it when you enter return.

The project is set up for Pipistrello but you should be able to change it to any Papilio board or the Mojo board by changing the project property to the correct FPGA part and modify the ucf file.

For the Papilio boards you also need the change the clock frequency parameter at the top of the verilog file.

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