bleedinggums Posted November 3, 2013 Report Share Posted November 3, 2013 hi! i bought the papilio mainly because i want to use it in my product. one of my product requires a deserialiser. the fpga seems perfect for this application. i went for papilio as i wanted to use port c for the input data and use ports a and b to output data in parallel. however, i encountered some problems using it. first of all, when i want to create the design, i get this pesky error message. " ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /clock site pair." my signal consists of BitClock, Data and etc. the data will synchronise with BCLK. i wanted to use P98 as BitClock. naturally my program works on "rising_edge(BCLK)". but it seems i can't use P98 for this purpose.i tried a few other pins and it seems i keep on getting other errors related to my choice of pin for BitClock. any suggestion here? thx! bgps: i scoped and i can't get any output at all. i suspect it's related to this 1018 error. Link to comment Share on other sites More sharing options...
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