First official release of the Papilio Schematic Library!

Jack Gassett

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Hello everyone, we have some exciting news today, the first release of the Papilio Schematic Library is ready to go!


Ever find that you need just one more serial port, or SPI master, or PWM? Wouldn’t it be nice to add any peripheral you could imagine to your microcontroller? Sigma-Delta audio DAC’s, Stepper Controller’s, Commodore 64 audio chips? Well look no further, the power of the Papilio FPGA removes the limitations imposed by static hardware and the Papilio Schematic Library provides the building blocks you need to draw your custom microcontroller in a schematic editor! No more searching for a new board because you are one serial port shy of finishing your project, the Papilio can adjust to your needs, not the other way around.


VHDL skills not required, if you can draw up a schematic then you can use the Papilio Schematic Library in no time. But don’t worry, if you want to dive into the VHDL then you can simply push into any of the schematic building blocks and study or modify the underlying VHDL code. How about Verilog you say? Sure, schematic building blocks can be made from VHDL, Verilog, or even a schematic – no limits here.

Take a look at the Papilio Schematic Library Getting Started Guide and get cracking with your own designs today. icon_smile.gif

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This is great stuff!  I did an SOC using the logic start megawing for the Papilio Pro.  Building an SOC using the schematic editor was something that I wanted to do, but couldn't quite connect the dots.  The library + tutorial + video made it very easy to do.  I was able to build sketches and make use of the SOC after uploading.  


I'd like to see many of the open core wishbone compliant components added to the library.  Maybe we could even get an open core library which has them in it.

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Great! Glad to hear that it was useful. :)


I started making a tutorial about adding multiple Uarts and I ran into some serious limitations with the 1.0 design. So I've spent the last couple days reworking the schematic library to address the problems I had.


First of all the wishbone slots were too close together and secondly all the buses for the wishbone slots removed a lot of flexibility. So I made a first attempt at packing all of the wishbone buses into a record. This means that each peripheral will be connected with two buses instead of the 10 or so before. Unfortunately I discovered that the schematic editor has no idea what a record is and converts the ports to a single signal! This fails pretty spectacularly...


I had to get a little bit ugly and pack all the buses into an array of signals and then unpack them into a record. The VHDL code is awkward but it accomplishes the desired result, wishbone peripherals can be connected with only two connections now.


The third, and most important, reason for getting the connections down to two is that it makes it much easier to generate schematic symbols. With all the wishbone buses as separate entities it was a very tedious and error prone process to get all of the wishbone connections moved to the top of the schematic symbol in the correct order. With this new improvement it only requires moving two pins... Much better.


There should be a new and improved 1.1 release coming in the next couple days.




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