SIMULINK: SW/HW Hardware Co-Simulation

[nick.avlonitis@gmail.com]

Hello everyone,

 

We have successfully used  MATLAB/Simulink in order to build a model, compile it and upload the bitstream to a Papilio One 250K.

 

However, we ran into a problem when we tried to use software / hardware co-simulation with the Papilio One FPGA-in-the-loop. More specifically, in order to setup the co-simulation we are required to enter the JTAG options:

a) Boundary Scan position (this is the position of the FPGA in the JTAG chain)

IR lengths (the length of the instruction registers for all devices on the JTAG chain). 

 

I tried to use the auto-detect option but no luck. 

My questions are:

1) Has anyone managed to use software / hardware cosimulation with the Papilio One 250 K

2) What are the correct values / settings for (a) and (

 

Thanks

 

Nick

 

 

 

 

 

 

[Jack Gassett]

Hmmm, this is interesting. I remember looking at it once, but I think it is pretty expensive unless you are at a university so I didn't go into it much. Would be really cool to have it working though...

 

I'm guessing that its the FT2232 chip that is getting in the way here. Does the simulink software support the FT2232? You need to send a command to the FT2232 to put it into JTAG MPSSE mode, maybe that is not happening. 

 

Jack.

[Jack Gassett]

Oh, your name also seems familiar. Have we ever met at a Maker Faire or somewhere?

 

Jack.

[nick.avlonitis@gmail.com]

Hi Jack,

 

I was hoping that Simulink could talk to the FPGA via the COM port the FTDI driver creates.

 

Would a possible solution be to by-pass the FT2232 and talk directly to the FPGA? Do I need a JTAG programmer for that? Would there be an interference from the FT2232 when I will try to talk to the FPGA?

 

 

Regards,

 

Nick

[Jack Gassett]

Nick, the FT2232 has two channels, A and B. Channel A has what is known as a MPSSE engine which allows it to become any kind of serial based device, either JTAG controller, SPI master, or a simple COM port. Channel A is connected to the JTAG ports of the Spartan 3E chip and if Channel A is used then it will only have an effect if Channel A is used as a JTAG controller. By default the FT2232 acts as a virtual COM port but it is not connected up as a COM port, if you open Channel A and try to use it as a COM port it will have no effect because the pins from Channel A of the FT2232 are connected to the JTAG pins of the FPGA. In order to use Channel A as a JTAG controller your software has to be aware that a FT2232 chip is being used and then set the MPSSE engine into JTAG controller mode.

 

Channel B does not have an MPSSE engine and it is connected to the Spartan 3E to be used as a virtual COM port. If the simulink software can communicate over a serial port rather then a JTAG port then you should be able to generate a bit file that includes the simulink VHDL code and have it connect to pins P88 and P90 as detailed in the Papilio One Hardware Guide. Then you would need to have Matlab open up the second COM port, which is Channel B, in order to communicate to the COM port based simulink implementation. I don't know that it can work this way, I'm just saying that if its possible that's how it should work. It would probably be easier then trying to add support to put the FT2232 Channel A into JTAG mode.

 

Do you have any links to documentation that explain what needs to be done?

 

Jack.

[nick.avlonitis@gmail.com]

Hi Jack,

 

The first test I performed in Simulink is to use pins P88 and P90 to communicate to the Papilio and I can confirm this works. For that I had to communicate to the COM port on Channel B. This is very easy to implement: Just use the Gateway In/out blocks and specify the pins under Implementation->Specify IOB location constraints (For those who want to try it out). 

 

The problem I have is when I try to use the FPGA in the loop. I was hoping that Simulink would use Channel A to talk to the FPGA but I haven't managed to make it work. In order to setup the board to be used in the co-simulation I need to specify ( I am not sure why?):

a ) Boundary Scan position (this is the position of the FPGA in the JTAG chain)

b ) IR lengths (the length of the instruction registers for ALL devices on the JTAG chain).

I am missing the above info.

 

Regards,

 

Nick

[Jack Gassett]

Ok, does the simulink software indicate that it supports the FT2232 anywhere? If it does not then entering the correct Boundary Scan Position and IR Length is not going to work.

 

As far as what those settings should be. The Spartan 3E is the only device on the JTAG chain so the Boundary Scan position should be 1. Since it is the only device on the chain the IR length is the Boundary Length of the Spartan 3E device you are using which can be found in the BSDL files.

 

For the Spartan 3E 250K used in the Papilio One the Boundary Length is:

attribute BOUNDARY_LENGTH of XC3S250E_VQ100 : entity is 440;

For the Spartan 3E 500K used in the Papilio One the Boundary Length is:

attribute BOUNDARY_LENGTH of XC3S500E_VQ100 : entity is 588;

Even with the correct numbers if there is no support for the FT2232 chip then this is not going to work. You can ask Mathworks to add support for FT2232 based devices.

 

Or you can purchase an external JTAG programmer that is officially supported by the Mathworks tools, I'm assuming the official Xilinx JTAG programmers probably are, and use the JTAG pins on the Papilio One to bypass the FT2232 chip. You can learn more about how this works in the forum.

 

Jack.