mkarlsson Posted October 2, 2013 Report Share Posted October 2, 2013 A new version of the Open Bench Logic Sniffer code is now available for Pipistrello. This version has the capture buffer increased to 64 MB by using the onboard LPDRAM instead of using internal BRAM. The capture rate is still the same, i.e. it still support 200 MHz 8 and 16-bit capture as well as 100 MHz 32-bit capture. The serial communication speed is set to 921600 baud. The original SUMP protocol unfortunately has a capture size limitation (in both hardware and software) to a maximum of 256k samples (512k samples in mux mode). This version of the verilog code has an alternative set of capture size registers that will allow up to 256M samples. However, the SUMP client on the PC must be modified to take advantage of the new registers so I have modified JaWi's OLS client to allow longer captures. BTW, the bit file will also work with the current release of the SUMP client but with the capture size limitation mentioned above. Here is a link to a zip file that has the bit file, the full Xilinx ISE project and the modified version of JaWi's OLS client:http://www.saanlima.com/download/pipistrello-v2.0/Pipistrello_OLS_64M.zip Enjoy! BTW, if anyone is interested in using the built-in DRAM memory controller in Spartan-6 parts this code might be a good starting point. It's setup to use one 64-bit read/wire port but this can be changed by using different parameters when instantiating the memory controller block. Link to comment Share on other sites More sharing options...
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