Encoder tests


F6EEQ

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I tried the rotary encoder example from XILINX and I found a curious problem.

 

I had my LS normally plugged, and I linked the encoder wires to the VGA plug because this was the only outlet easily available (on VSync and HSync) and they were pulled up high via the UCF config.

It did not work.

So after hard :P thinking, I decide to slide the LS in the "led and switch only" position on wing C, and to connect the encoder to some place in the free wing, UCF adapted but everything remaining the same.

Suddenly everything was running well.

 

I suppose the 2 serial resistors in the VGA connection (82 ohms) although small brought perturbation to the pull up circuit.

 

I have another question to this circuit.

 

In the VHDL sketch there are successive affectations: for insatance A<=B<=C to handle encoder signal and internal signals.

I understood this is to add registers, and prevent glitches but the process is a little bit hard to understand.

It was also explained in the encoder example of FPGA 4 fun, but it still difficult to me.

 

 

Well, enough for today!!

 

 

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