Wishbone and SDRAM

[fcharby]

Hello all,

 

I have read a lot of posts, a lot of documentation, watched videos and I am still a little confused. I have downloaded the ZPUino source code and gotten it to compile in ISE. I can load sketches, etc, etc...It is all very beautiful and amazing and I'd like to integrate it to my project so that I can add more features to it.

 

What I am wondering now is how I can customize this to fit my needs. I want to monitor a data bus using pins on my FPGA and on a specific trigger, write the data to RAM. I have come to realize that using SDRAM is very complicated so I was hoping to add my logic bloc as a wishbone peripheral of some sort that is hooked to the same wishbone bus as the SDRAM so that the data is writable from my bloc and readable from my sketch code.....

 

Is that even doable? If so, does anyone have any pointers to get me started? If not, other suggestions are appreciated!

 

Also, my wording here might be confusing here, let me know if I need to clarify....

 

 

Thanks everyone (and many more thanks to alvieboy and hamster for the code, the documentation and much more).

[Jack Gassett]

Hello,

 

This is something that is on my radar, what I want to do is turn the OpenBench Logic Analyzer core into a wishbone core that can plug into the ZPUino's wishbone slots. This coupled with the schematic based builder that I'm working on would allow you to make a custom Logic Analyzer that would be connected any way you desire according the the schematic you draw. I envision that the OLS core would use the internal BRAM available in the Papilio Pro's LX9, but I guess it would be possible to store it in the SDRAM at slower speeds, probably 30-40Mhz and below. My intention is to make it so you can trigger captures from a sketch and then spit the captured data out to the OLS client.

 

I think this is going to be really, really sweet but there are some things that need to be finished first. Namely the schematic editor, once I get that released and documented then the OLS wishbone core is the next goal...

 

If you want to take a stab at turning the OLS core into a wishbone core right now we can try to support you the best that we can in that endeavor.

 

Jack

[fcharby]

Actually, that would probably fit my needs as well, although we could say my goal was kind of a subset of the whole OLS thing. I have no objections taking on a bigger project if I can get a little help to put me on the right track.

 

The problem right now is I don't have a thorough enough understanding of the wishbone platform to know what can and can't be done. My original question was to make sure that the SDRAM could be accessed separately from the ZPUino core so that the write speed doesn't get slowed down by code execution...kind of like the BRAM blocks inside the FPGA can have separate channels.

 

Anyway, I'd be happy to help out any way I can and if working a little harder on this means I can add extra functionality to my project as well as share it with others, all the better!

 

Thanks.

[Jack Gassett]

I'm not totally sure about the ZPUino and OLS core accessing SDRAM memory, I don't think it would be a good idea, but Alvie can answer that for sure. I see two approaches for sure:

 

1) The ZPUino on the Papilio Pro leaves a lot of BRAM blocks available from what I know. There is around 75K Bytes of total BRAM blocks available and the original OLS only uses 40K Bytes. So the free BRAM in the Pro could be used. I'm not sure how much BRAM Alvie uses for caches but I think there is probably at least 40KB of BRAM free still.

2) Have the OLS capture to a small BRAM buffer and then have a sketch copy from BRAM to SDRAM. You would sacrifice the speed that could be captured at, internal BRAM can go up to 200Mhz, but it would simplify your memory usage since you would be piggybacking on the ZPUino's SDRAM controller.

 

Jack.

[hamster]

The -7E speed part can run at 133MHz, but the required timing will be pretty hard to hit with an controller that is implemented in the FPGA fabric, so I guess a FIFO buffered 100MHz / 8 channels would be about the best you could capture to SDRAM.

 

The 200MHz/8 channels or 100MHz/16 channel or 50MHz/32 channel would require more bandwidth that the SDRAM has when running at 100MHz - transfers burst to 200MB/s, but you have to discount for row activation / precharge and for refresh.  

 

 

If it 133MHz can be achieved then 200MHz/8 or 100MHz/16 is just about possible. Still, 100MHz/8 channels, with 8M samples  would rock!

[alvieboy]

The better idea here is to have a FIFO (a 2K block ram), and have it connected to the master DMA interface (which then accesses the SDRAM), and perform size-limited write bursts. Since many things must access memory, I guess a good "speed" would be about half of the bandwidth, like 50M transfers/s of 16-bit size.

[fcharby]

Can you give me a little bit more information on how to use the DMA wishbone of the ZPuino? Or possibly a quick example?

 

Maybe there is documentation somewhere and I haven't found it...sorry if that's the case...if there is, just let me know where it is and I'll get working on this right away!

 

Thanks for the input.

[alvieboy]

The DMA port complies with Wishbone 2B in pipelined mode.

 

One example of its use is the VGA interface:

 

https://github.com/alvieboy/ZPUino-HDL/blob/master/zpu/hdl/zpuino/vga_zxspectrum.vhd

 

Make sure you don't starve the DMA port. That would cause the CPU to halt because it cannot access memory nor program.