fcharby Posted September 23, 2013 Report Share Posted September 23, 2013 Hello all, I have read a lot of posts, a lot of documentation, watched videos and I am still a little confused. I have downloaded the ZPUino source code and gotten it to compile in ISE. I can load sketches, etc, etc...It is all very beautiful and amazing and I'd like to integrate it to my project so that I can add more features to it. What I am wondering now is how I can customize this to fit my needs. I want to monitor a data bus using pins on my FPGA and on a specific trigger, write the data to RAM. I have come to realize that using SDRAM is very complicated so I was hoping to add my logic bloc as a wishbone peripheral of some sort that is hooked to the same wishbone bus as the SDRAM so that the data is writable from my bloc and readable from my sketch code..... Is that even doable? If so, does anyone have any pointers to get me started? If not, other suggestions are appreciated! Also, my wording here might be confusing here, let me know if I need to clarify.... Thanks everyone (and many more thanks to alvieboy and hamster for the code, the documentation and much more). Link to comment Share on other sites More sharing options...
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