Capture data to SRAM and retrieve later


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I have a experience with microcontrollers and embedded systems, but I am entirely new to the world of FPGAs. I have an idea for a project that I'd like to do and I think a FPGA is the way to go, although I can't confirm that the Papilio Pro is the right board for it.


Basically, I want to monitor a bus of 30+ channels and capture data on a specific trigger, that data would be stored in RAM and retrieved later probably via the serial FTDI chip, which makes the most sense since it's already available on the board.


Is anyone able to tell me if this project is feasible with the Papilio Pro?


Thank you in advance.

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That sounds exactly like the Gadget Factory Logic Sniffer / SUMP logic analyser (which has a nice Java GUI), or my little hackky Cheapscope project (source code at


Depending on your capture speed you it might be possible to stream the data into the Papilio Pro's SDRAM. The SDRAM has only limited bandwidth (200MB/s IIRC) and lot of interruptions (refresh, opening/closing rows and so on) that might restrict you to maybe 50% of that (100MB/s or 1000Mb/s, so sampling at 33MHz for 32 channels). I might be a bit pessimistic, and you might get enough bandwidth to capture 32 bits @ 50MHz.


This is far below the bandwidth of the on-FPGA block ram, which has well over four times that each of its 32 blocks (each could be configured to be 32 bits and run at 200MHz)!


The Pro's 64Mb SDRAM would be enough for about two seconds of 32-bit / 33MHz capture , but playback over the serial port will be quite slow.... but if you run it at a very high speed (1Mb/s) it would take well over a minute (as each byte has a 25% overhead for start and stop bits).


All sounds feasible. 

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Yep as Hamster said, what you want to do has already been done (bummer eh?) so you could use the same code as the Gadget Factory Logic Sniffer on the Papilio using only internal BRAM and then take advantage of the nice Java GUI for the SUMP. It's very important to remember that the FPGA can only accept 3.3V signals, the Logic Sniffer has a level translator chip on it's inputs, so if you use a Papilio, you have to use a level translator wing, or just only sample 3.3V logic

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Yes, I was aware of the logic sniffer project but it has a few limitations that can't be circumvented such as the amount of samples that can be captured....


My problem requires another solution, I'll be more specific, one of the buses I currently want to monitor is between a microcontroller and a parallel memory. On this specific board, there is a lot of activity on the bus because there are other devices connected to it but all I care about is the memory and what is read or written to it, so my idea was to use a FPGA to do all the work instead of having my computer download a crazy amount of captures to analyse the content and figure out what is what. With a FPGA, I could passively monitor a bus and reconstruct the content of a memory somewhere inside the SDRAM or even the FPGA memory. I also need to a able to deal with memories of a few megabytes...


I could leave my device alone for a few minutes and let it collect data while not having to worry about overflowing....


I don't know if that changes anything, I guess this is still doable. I appreciate all the tips you guys have given me so far.



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Well, I ended up buying the board anyway with some wings and other components, it's not that expensive, plus it looks like a lot of fun. I'll figure out what I can and can't do with this type of board and then I'll see where that takes me...


Hamster, I also downloaded your tutorial which I will follow along from beginning to end. This will be a great journey and I look forward to it!


Thanks all for your help.

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  • 8 months later...

BTW, I'm using similar boards in the lab to listen to bus traffic, detect what I'm interested and dump it out to USB serial.

As long as the average output rate is below USB baud rate, it only needs a FIFO, which is the easiest way.

The built-in USB (on-board FTDI chip) works well enough for me.


You can find an example project on this site as "really dumb MIDI monitor". Uart for incoming MIDI, Fifo to handle peak traffic, Uart for USB.


Before going for crazy bandwidth and capture memory, I'd rather write some RTL that filters through the data and reports just what I need. Writing state machines isn't that hard. And it's easily controlled via USB in the other direction (i.e. use teraterm). For example, I usually have only one or two switches, simply use the LSBs from the last incoming byte.


You also have the option of migrating the design later to a Spartan 6 LX 45 board for more on-board memory, but none of those I own are as user-friendly as the Papilio Pro with custom bitstream loader.


Capturing at digital voltages below 3.3 V may be possible (i.e. 1.8 V) For inputs, just set it in the constraints file; you can't drive the signals, though.

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