alex Posted August 29, 2013 Report Share Posted August 29, 2013 Hey, what's up, the forum's been so quiet for the last week, are you all hibernating? If you are, here's a nice way to pass the time. Make a hot cuppa of your favorite beverage and sit back and enjoy this link to a nice half hour video I found of Colin, showing a step by step way of building a FIR filter. He is using Vivado for HLS (high level synthesys) to turn C code into VHDL/Verilog and then bring the output created by Vivado into the old school ISE environment to synthesize the FIR for a Spartan 3 FPGA. By being careful enough not to generate Virtex/Artix specific blocks, this technique can be used to turn almost any C code into functional synthesizable RTL for FPGAs not technically supported by Vivado. Pretty cool if you ask me. Link to comment Share on other sites More sharing options...
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