System clock

[F6EEQ]

hi there!

 

Thanks to this wonderful forum and Hamster's book + other nice FPGA links, I began to move my way in this jungle.

Slowly, because I have not enough time to go very deep, but at least I had some leds blinking in all possible order!!!

 

I understood how to derivate a simple "slow" signal from the 32 MHz clock by counting some bits, even bytes, because to get a visible rate you really have to count a lot.

 

I was wondring if it is possible to derivate a slow signal by "harware", I mean to give a sort of command to the FPGA which could give magically the right frequency you need.

I read XILINX UG382 (got the link from a post iin this forum), but I must admit that I'd rather read a chinese text :P .

 

So I have two questions:

• is this possible?
• if yes, is a tuto or a simple VHDL sketch available so that I understand the basics.

I do not wish to go too deep for the moment, but just understand. In the XILINK doc I did not see any VHDL or VEROLOG sample.

 

Thanks for your help.

[Jack Gassett]

Hey there,

 

Indeed there is a way to derive any clock speed you want using the DCM (Digital Clock Manager). There are four DCM's in the Spartan 3E and two DCM's and two PLL's in the Spartan 6. So you can generate quite a few custom clocks with those resources.

 

Take a look at this tutorial about how to use DCM's.

 

Jack.

[F6EEQ]

Thanks Jack,

 

the WIKI is full of hidden treasure, but I almost always forget to have a look there!!

[F6EEQ]

This is a nice example of what to do, but to be very honest, I would have prefer some text rather than a video.

 

I know I'm 63 and not very keen to modern learning process!!!

I still very much prefer reading than watching a video. I've printed almost all the stuff from Hamster or other sites, because I like to have the text under the eyes while I'm typing the programs or trying to calculate some weird conversion.

 

Well, when it's over 100 pages, I make the effort to read online. Thats the case for the VHDL e-book and the Mc logic design (more than 800 pages!!).

 

Anyway, your tuto is perfect and I will try it at the next opportunity.

 

Do you know (or did you try) to which low frequency you may go down? In you tuto you're going up.

 

Well, now I will leave home for summer holydays, and I must wait September to have a new try!

 

Thnaks again.

[alvieboy]

F6EEK:

 

you don't want to go down... cause you don't need to.

 

use the "CE" ability of all synchronous elements to control when data is moved from one sync element to another.

 

Meaning...

 

if you have a "1MHz" clock, and a 3-bit counter (counts from 000 to 111 == 7), and use the "and-ed" bits to control the "CE", you have a design running at 1/8 clock speed.

 

Other tricks exist, let me know if you want to know them.

 

But inside the FPGA there are lower limits to the frequency. See the AC/DC switching for the internal clock generators (DLL/PLL).

 

For example: the PLL on Spartan3 requires a VCO frequency between 400MHz and 1GHz.  There are also lower frequency limits, check the corresponding datasheet.

[Jack Gassett]

I hear you about the videos, I would like to get the videos transcribed so there is a video and text. Going forward that is my approach, but its hard to get the time to go back to the already existing videos.

 

I just looked at the Spartan 3E datasheet and the DCM will go as low as 5Mhz.

 

Jack.

[F6EEQ]

Hi there,

 

thanks for your answers.

Now I'm back from vacation, and I will try to play with the clocks

 

Thanks Alvie for the hints. I probably will come back later.

[F6EEQ]

I tried to follow the video, but when I wish to add a new source, there is nothing looking like a DCM source.

 

Is there a special module to download from XILINX??

I use version 14.3 of ISE.

 

Thanks

[hamster]

Hi F6EEQ.

 

You might be seeing the side effects of this installer bug:

 

http://www.xilinx.com/support/answers/53695.html

[F6EEQ]

OK and thanks for the info.

 

I installed the soft with a CD provided by XILINX, so I had a full install...

 

Apparently this is solved with 14.5.

 

I will download 14.6... if I succeed to load it with my poor internet connection.