Digilent PMODI2S


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I just got a Digilent PMODI2S to use as an Audio DAC to play with, and just wasted the best part of the weekend due to a really annoying reason.


Trace the signals on the schematic (http://digilentinc.com/Data/Products/PMOD-I2S/PmodI2S_sch.pdf) from the PMOD to the DAC:  - yep, the schematic is correct! :-( Grrrr


Having said that, 16 bit stereo at 48,828 Hz sample rate is pretty sweet :-)

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Hey I have that PMOD as well, I just haven't had a chance to use it yet.


When you say the schema is correct, which part do you refer to? The signals on the chip side match the datasheet but the ones on the connector side are in reverse order. Are you saying the wiring is correct and the labels on the connector side are reversed? Would be good to know, or maybe post some sample code on your wiki save us all the trouble :)  Good find!


I myself am fighting with someone else's stubborn code that seems to produce the expected results during simulation but fails to work when run on the FPGA despite the design meeting timing, no removed logic, no errors and no unusual warnings. I've never encountered that before, usually the simulator catches everything.

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The pin labelling the reference manual is wrong, and the schematic is 100% accurate.  - i.e:


Although the manual has pin one as SDIN, it is in fact connected to the MCLK on the DAC.

Although the manual has pin four as MCLK, it is in fact connected to the SDIN on the DAC.


Maybe we have the only two ever sold? :-)


For your design, have you check for needing pullups on any tristates, or possibly IO standards? the usually stuff me up.... some FPGA models have very week pullups, and may need an external resistor.

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Nah my problem is not related to I/O, it is all internal to FPGA, eg an output from an internal VIA 6522 chip which should be counting 7..0 seems to be stuck on 0 even though in the simulation it is behaving correctly. This made me suspect the CPU is not running, but then I routed the CPU clock and some address bus lines to LEDs on the board I can see the CPU clock is 1MHz as expected and the address lines are toggling so the CPU appears to run but the VIA output is still stuck even though it works in the simulation and I make no changes to the design, I literally simulate it and it works fine then double click generate bit file and upload it to FPGA and... nada. It's got me stumped for now. If you're interested we can move this to email as it doesn't relate to the topic in this thread. I hope I haven't found another bug in ISE.

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