First design... and first question!


F6EEQ

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Hi there,

 

I had time his evening to jump right in the middle of FPGA fun with my new PRO and LogicStart!

So I've downloaded all drivers, and it seems to work perfectly.

 

I've loaded the Quick Start bit file, and it works (I tried only to light the LEDS, not the TTY stuff)

 

I've loaded the first project from "Introducing to..." with XILINX ISE, and the two LEDS light with the buttons as expected.

However there is something strange: the 7 segment are always lighted.

 

If I push on "RESET", after a while all  8 LEDS are on, then off, then all even LED blink, which is what was intended with my first downloaded config (Quick start bit file) and here the 7seg's are not lighted.

 

It seems that the initial program stays in the EPROM even if I've downloaded another one.

 

If I reload my 2 LED config all starts again.

 

Strange isnt'it?

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The seven segment display will always glow softly - the default behaviour for an unused FPGA is to have a weak pull-up to high. This turns on each segment's transistor a little, and then maybe a mA of current from the segment pins flows through each digit's segments.

 

When you download a bit file you have the option to store it in eeprom, or just reconfigure the FPGA. Storing in the eeprom is slower, but the design will persist over power cycles.

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Hi Hamster,

 

thanks for kind answer.

 

OK for pull-up.

 

This night I awoke and suddently I had a flash of intelligence!! I realised what you said that you have the choice to load either FPGA or SRAM. In my excitment in succeeding to light a LED :P I had forgotten this small option window. So you have confirmed this.

 

Now I'm sure everything is OK and real work may begin!

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After some reflections, I have another question.

 

If pull-up can light the 7 segs, it uses some mA or µA. Isn't it bad in term of powed dissipation? If you play only with the swithched/leds, may be it's better to turn to your idea of using the LogicStart with LED's on wing A/B to save some power?

 

Is there a way to force unused pins to pull-down?

 

Thanks.

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Yes, it does use a little power - but only a little mind you.

 

The easiest way is just to declare the anode pins in the UCF file (pins for the Papilio One):

 

NET "SS_ANODES<0>" LOC="P67" | IOSTANDARD=LVTTL;
NET "SS_ANODES<1>" LOC="P60" | IOSTANDARD=LVTTL;
NET "SS_ANODES<2>" LOC="P26" | IOSTANDARD=LVTTL;
NET "SS_ANODES<3>" LOC="P18" | IOSTANDARD=LVTTL;

 

then explicitly set them to be always '1' in the design (they are active low).

 

   SS_ANODES <= "1111";

 

The locations needed for other boards can be found at  http://papilio.cc/index.php?n=Papilio.LogicStartMegaWing#segment

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  • 2 weeks later...

Just got my logic start (for my papilio pro) today and I got my first working bit file created.

It is a simple 4 bit adder (switch0 to 3 and 4 to 7).

The switches control segment q3 and q4.

q2 is a carry bit and q1 is the sum.

joystick press is a reset and shows that the segments are multiplexed.

 

Only issue that bothered me is the UCF file had to be modified by taking out <pullup> on TX and Flash_SO to work with Aldec ActiveHDL student version.  What will this do? I am new to FPGA design, and I am worried with others designs and no pullups i may fry some leds or worse, damage the chip.

 

I also had to remove period=31.25ns from clk.

 

Thanks for having such a great product and forum.

 

edit -- commented out unused pins in ucf file

sum_carrybit_add4_add4.bit

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