Ppro not storing bitstream in flash


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EDIT: fixed, needed to change fpga startup clock to CCLK instead of JTAG.


I'm having some trouble with my ppro loading its program from flash. I've tried papilio loader 2.1 and 2.4, and write to spi flash runs, and looks like it has worked from the pc end, as it says: 



JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9Using devlist.txtJTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9Uploading "C:\Program Files (x86)\Gadget Factory\Papilio Loader24\programmer\bscan_spi_xc6slx9.bit". DNA is 0x19413851fc72cbfeDone.Programming time 547.0 msProgramming External Flash Memory with "G:\Downloads\LCD-Driver-0.1\LCD-Driver\controller.bit".Found Macronix Flash (Pages=32768, Page Size=256 bytes, 67108864 bits).Erasing    :Doing Partial Erase......OkVerifying  :......PassProgramming :......OkVerifying  :......PassUsing devlist.txtDone.SPI execution time 17254.4 msUSB transactions: Write 17348 read 17179 retries 0JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9Using devlist.txtISC_Done       = 0ISC_Enabled    = 0House Cleaning = 0DONE           = 0

However, afterwards the board just sits doing nothing. writing straight to the fpga works fine. This is on win8 x64 if that makes any difference. If anyone could help it'd be appreciated.

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I've tried with xc3sprog in a vm, and get this:



james@ubuntu:~/Papilio-Loader/xc3sprog/trunk$ sudo ./xc3sprog -c papilio /home/james/controller.bit -v -R -I ./bscan_spi/bscan_spi_lx9_papilio.bit 
XC3SPROG © 2004-2011 xc3sprog project $Rev: 691 $ OS: Linux
Free software: If you contribute nothing, expect nothing!
Feedback on success/failure/enhancement requests:
Check Sourceforge for updates:
Using devlist.txt
Using cablelist.txt
Cable papilio type ftdi VID 0x0403 PID 0x6010 dbus data 00 enable 0b cbus data 00 data 00
Using Libftdi, Using JTAG frequency 6000000
JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9
JEDEC: ff ff 0xff 0xff
unknown JEDEC manufacturer: ff
Created from NCD file: controller.ncd;HW_TIMEOUT=FALSE;UserID=0xFFFFFFFF
Target device: 6slx9tqg144
Created: 2013/05/07 19:41:54
Bitstream length: 2724832 bits
Programming not yet implemented
USB transactions: Write 6 read 4 retries 8
I don't know if the unknown manufacturer bit is the relevant part, but it looks dodgy.
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Fixed it :) I had to right click on "generate programming file", go to startup options, and set the FPGA start up clock to CCLK instead of JTAG. I have no idea why it was set to that in the first place :s maybe this is something that should go in the faq/ papilio loader should complain if the .bit file has the wrong option for this?

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Yeah I guess so, I haven't tried anyone else's .bit files. It's a really strange issue, I'm so chuffed I worked it out, it took me reading a lot of the lx9 datasheet and guessing. It surprised me that ISE didn't warn me, since it warns about other stuff, and starting off the jtag clock seems like an unusual configuration.

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