austinmags Posted April 30, 2013 Report Share Posted April 30, 2013 I was running through the FPGA tutorial by Hamster; hit a hard stop on the VGA chapter. I'm essentially trying to generate a 640x480 60Hz signal which displays a red screen. The monitor consistently reports no signal; I've verified the cable and monitor work independently of the board. My clock appears to be correct; I've used a variety of test configurations to validate I have a 25MHz clock. I'm now measuring signals directly out of the VGA connector on the Logic Wing; the VSYNC signal has been verified, but HSYNC is not produced on the expected VGA connector pin (13) given the Papilio Pro constraints. (I'm measuring using a voltmeter - get 3.3 volts when measuring vsync, 0 when measuring hsync). I'm wondering if either I have a defective test, board, or incorrect constraints for the Papilio Pro / Logic Wing. Any help / guidance would be much appreciated of how to proceed. My diagnostic code:entity VgaDiscoverer isPort (clk : in std_logic;vga_vsync : out std_logic;vga_hsync : out std_logic;switches : in std_logic_vector(7 downto 0));end VgaDiscoverer;architecture Behavioral of VgaDiscoverer isbeginprocess(clk)beginvga_vsync <= switches(0);vga_hsync <= switches(1);end process;end Behavioral; My constraints:NET CLK LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns;NET switches(0) LOC = "P114" | IOSTANDARD=LVTTL;NET switches(1) LOC = "P115" | IOSTANDARD=LVTTL;NET switches(2) LOC = "P116" | IOSTANDARD=LVTTL;NET switches(3) LOC = "P117" | IOSTANDARD=LVTTL;NET switches(4) LOC = "P118" | IOSTANDARD=LVTTL;NET switches(5) LOC = "P119" | IOSTANDARD=LVTTL;NET switches(6) LOC = "P120" | IOSTANDARD=LVTTL;NET switches(7) LOC = "P121" | IOSTANDARD=LVTTL;NET vga_vsync LOC="P99" | DRIVE = 2;NET vga_hysnc LOC="P97" | DRIVE = 2; Link to comment Share on other sites More sharing options...
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