cospan Posted April 3, 2013 Report Share Posted April 3, 2013 Hello, I'm designing a development board and I would like to include a 16bit wing interface. There are certain pins on FPGAs that is optimized for clock input. Is there a standard pin location on the wing that is specified as a clock input? I went through the Papilio Pro schematic and found the following pins were attached to GCLKs W1 A2W1 A3W1 A12W1 A13W1 A14 W1 B4W1 B5W1 B10W1 B14W1 B15 W2 A9W2 A10W2 A11W2 A12W2 A13W2 A14W2 A15W2 A16 Which is a surprising number of GCLKs (awesome!). It looks like the pin that is common to them all is 14. So if I were to map an input clock enable pin on at least 14 would this work for wings? Dave Link to comment Share on other sites More sharing options...
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