Unclocked processes


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Hello experts


I've seen in my travels different coding styles and for the life of me I can't decide what is the correct way or the better way to express the HDL.


Take for example this coding style, used heavily in Mike Field's FPGA Arcade HDL:

architecture behavioral of top isbegin  process (a1, a2)  begin    b <= a1 xor a2;  end process;end behavioral;

Perfectly fine piece of HDL, all changing inputs are covered in the sensitivity list, output "b" changes whenever any of the inputs "a1" or "a2" change state.


Then there is the coding style I usually use:

architecture behavioral of top isbegin  b <= a1 xor a2;end behavioral; 

Again, very simple combinatorial HDL, doesn't bother with process statement and sensitivity list, simple assignment.


If I bang either one of these styles in ISE and view the RTL schematic produced, they are identical in each case, so not sure why anyone would use the longer "process" statement for combinatorial logic when a simple one liner assignment seems to suffice.


Please enlighten me.


EDIT: Here is an actual real life example from FPGA Arcade code, all of these synthesize to the same RTL schematic:


FPGA Arcade original code:

  p_bit_mask : process(I_DATA)  begin    bit_mask <= x"01";    case I_DATA(3 downto 1) is      when "000" => bit_mask <= x"01";      when "001" => bit_mask <= x"02";      when "010" => bit_mask <= x"04";      when "011" => bit_mask <= x"08";      when "100" => bit_mask <= x"10";      when "101" => bit_mask <= x"20";      when "110" => bit_mask <= x"40";      when "111" => bit_mask <= x"80";      when others => null;    end case;  end process;

Alternate "no process" statement way of writing it:

bit_mask <= x"01" when I_DATA(3 downto 1) = "000" elsex"02" when I_DATA(3 downto 1) = "001" elsex"04" when I_DATA(3 downto 1) = "010" elsex"08" when I_DATA(3 downto 1) = "011" elsex"10" when I_DATA(3 downto 1) = "100" elsex"20" when I_DATA(3 downto 1) = "101" elsex"40" when I_DATA(3 downto 1) = "110" else x"80" when I_DATA(3 downto 1) = "111" else x"01";

My preferred even more compact "no process" statement:

with I_DATA(3 downto 1) select bit_mask <= x"01" when "000",x"02" when "001",x"04" when "010",x"08" when "011",x"10" when "100",x"20" when "101",x"40" when "110",x"80" when "111",x"01" when others;

The last two examples can just be inserted anywhere in between the begin/end statement of your architecture without wrapping them in a process statement. 



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HI Alex - you mean Mike J's FPGA arcade. :-)  


And in practice all three forms are identical, and it is a matter of personal style. I have seen some really wacky examples where it sort of makes it a clocked assignment + async reset in single line:


q <= '0' when reset = '1' else d when rising_edge(clk);

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Here's what I use often, a mix of sync + async process:


type regs_type is record   r1: std_logic; -- one bit register   r2: std_logic; -- one bit registerend record;signal r: regs_type; -- Registerssignal i1, i2: std_logic; -- In Signalssignal o1,o2: std_logic; -- Out signalsprocess(i1,i2,r,clk)   variable w: regs_type;begin  w := r;  o1 <= i1 and i2; -- Async  o2 <= i1 or i2;  -- Async  w.r1 := i1 xor i2; -- Sync (see below)  w.r2 := (i1 and i2) xor i1;  if rising_edge(clk) then    r <= w; -- Synchronous assignment  end if;end process;
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