Getting the SUMP Logic sniffer running on Papilio One 250


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Hi! I hope this is the correct place to ask this. I am brand new to FPGAs and also to logic analyzers so this is probably just a noob problem but I haven't found any answers that have helped me.


I bought a Papilio One 250 and a buffer board. My goal is to record up to 16 channels of data (5 volts, hence the buffer board) to analyze (a microcontroller controlled sewing machine that has problems with the motherboard).


I can connect to the Papilio. I have loaded the quick start sketch and can see that it works (at least, it is sending data to Putty as it should. I don't have the B/Led wing to test output.)


For the logic analyzer, I am testing by connecting the Papilio to my computer and connecting the probes from the buffer board to a flashing LED on my arduino. I am using the latest "Quick Start" file in Windows XP (in a virtual machine on my Mac). So far, I can not get it to record the signal changing state from the arduino. I can tell that something is working because I can get a channel to go high when I have the ground probe connected to the negative lead of the LED and another probe connected to the positive. However, it does not change state as it should.


So, with discrete components, I would know how to go about checking it, but with the FPGA, I don't know where to go from here. I also tested Jawi's OLS client and can't get it to connect to my board at all. The problem is probably in my use of the client but I haven't been able to find any clear directions on how to use it so some pointers that way may solve the issues I have (I hope!)


Thanks for any help!

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Hello Unirambler,


Be sure to download the Sump Logic Analyzer QuickStart Package from here:


The Papilio Quick Start is different from the Sump Logic Analyzer QuickStart, it sounds like you might be using the Papilio Quickstart instead of the Sump one.



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Actually, I think it is working. Hamster gave me a hint to try recording all 32 channels first because of some quirks with speeds/settings/etc. When I tried that, it looks like it is working. I still need to test with more than one channel of data and different signal speeds... and figure out all of the settings and what they mean. :-)


One more question. I tried to use Jawi's OLS client (version and can't get it to connect to the Papilio One. Doesn't this client work with this board or does it need the logic sniffer board?



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  • 2 weeks later...

It's interesting that this thread should pop up.


I've been wondering if it would be possible to include the Logic Sniffer HDL into another project (on a board like the Papilio One 500 or Papilio Pro, which would have room for it and your project) and then use a Sump client as a ChipScope substitute for those of us using the WebPack tools.


In other words, I don't want to hook the probes up to external pins, I want to hook them up directly to the modules I'm working on in the FPGA.


Has anyone else already done this?

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yes, I've got a version of the AVR8 integrated with the OLS core somewhere... It is very possible, the biggest challenge is that you need to balance BRAM usage between your application and the OLS client. The Papilio One 250K does not have a whole lot of BRAM available.


The whole Benchy concept builds on this idea, making the OLS core a wishbone component that can be plugged into the ZPUino and lets you shift the probes around on the fly.



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