jbb Posted January 8, 2013 Report Share Posted January 8, 2013 I'm slowly working on my own (slow and basic) sdram controller while learning VHDL (I only did verilog before). I'm using a DCM block to generate a 100Mhz clock for my state model for this.It worries me that I might try to do too much logic and signals won't be computed in time before the next clock comes along which obviously will break things. I assume this is what the timing constraints are for though? To verify that your design will work at the speed of the clock. But I can't find any information about how to add constraints saying that a specific signal is generated using the 100Mhz clock rather than the 32MHz standard clock for example so the logic needs to be fast enough to work for that.Or rather I can find lots of information. Too much... And I don't know where to start. Can anyone either help me out with how to set up suitable constrains, or point me at an introduction to how to do this rather than the hundreds of pages of documents that tell you everything at once. (Which obviously I'll read once I understand the basics) Link to comment Share on other sites More sharing options...
This topic is now archived and is closed to further replies.