Recieved Papilio one...a few Q's about schematics.


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Hi Guys and Merry new year!

I received my Papilio500K yesterday and am just waiting for the Logicstart to arrive. :0))))))))))))

I have managed to get the quickstart file working very easily with ISE webpack. I didn't have a logicstart  so just attached an LED to GND and one of the even number pins. All worked and so did the serial port demo showing the AscII codes. All happy!

I then discovered the schematic editor on the webpack.

I did a boolean logic primer at college a few years ago as part of an audio systems course so I still remember all my ands ors nands xors etc ( even some combinational logic, de morgans and karnaugh!) but i'll have to do a recap. I would like to know how far one can go with using the schematic editor.. Is it possible to create your own components?

 Are there any good PDFs out there maybe by xilinx or others that could help me use the schematic way of programming?

I have the reference but it would be nice to do a few toots too..

Very excited to get the board. Roll on spare time from UNI work so I can get my head into the Papilio.:)




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Check out this thread, there is an AVR8 project posted there that lets you mess around with the AVR8 in the schematic editor, be sure to get the latest version.


I've actually started working on what I'm tentatively calling "Papilio SOC" which will allow you to build System On Chips solutions for the Papilio using the schematic editor. There is still a lot of work left, I'm in the exploration stage, but I see this as the final piece of the puzzle for the Papilio. My initial work has been very encouraging and I'm still trying to schedule the time to put the first revision of the system together. Once I do I will post it here to the forums.



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Hi Steve,


When I first started I used the schematic editor too. As I had a background in "magazine-style" hobby electronics schematic entry seemed very attractive. I spent many long nights building a VGA adapter using schematic tools. 


To answer your qns:

- You can create your own components. You add a new schematic, create connectors on it, then select something like "create component" from the Process menu. This then adds it to the component library for you to use in other schematics.

- I used the first 15 chapters of DIgilent's textbook that can be downloaded from, in either a VHDL or Verilog flavour.


However for anything other than the final wiring of components together I don't think that it is a good long-term plan.


When you start generating designs your productivity drops to close to zero as you try to make everything look visually "right" in the schematic.  Bugs are easy to generate - putting 'taps' on a bus is painfully slow, and when things don't snap together correctly your build fails even though the schematic looks accurate.  During your build phase and verification phase you spend all your time looking the obtuse VHDL or Verilog code generated by the schematic editor trying to figure out which random named variable carries which signal.


Your schematic design also has a lot of surplus metadata that is not used in generating the final FPGA bitfile - positions and segments of wires, location of components, bus names, signal connectors and so on.


The best advice I can offer is to play with the schematic editor a little to get the idea of how things work, then learn a HDL ASAP.

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Yes, Hamster has a good point. I envision the Papilio SOC system that would use the Schematic entry tool as a way for anyone to build SOC's without the overhead of learning a new language. However, I would never dream of trying to make any of the components that comprise the Papilio SOC library with the schematic entry tool, it would only be useful to connect components that have been defined with HDL together. HDL's such as VHDL or Verilog are the tools to define any serious functionality as the schematic tool will get very unwieldy very quickly. I do believe that it will be perfect to get people started with doing cool things with an FPGA and will serve as the bridge to learning HDL.


The Papilio SOC concept is to have a library of Soft Processors, such as the ZPUino and AVR8, and a library of components that can be connected to them schematically, such as audio, video, and uart chips. The schematic entry tool will be used to connect them together to build a custom SOC that does exactly what you need. Then people can experiment with VHDL to define new components.



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Thanks for the digilent links Hamster. Ive found the PDFs for VHDL & Verilog. From what I've learned so far I think I will be going down the VHDL route for now. 

The Papilio SOC sounds very cool indeed. I'm still  awed that its possible to synthesize and emulate other chips and systems on the Papilio..oard 

It makes me think about a particular sound chip I love. Namely the Texas instruments SN76477 synthesizer on a chip. It was a chip released in the late 70's containing a triangle wave oscillator, noise generator, lfo and ADSR and was used on the original space invaders and galaxians arcade machines. I have built Thomas Henry's SN voice design and have a very nice standalone SN voice synth with 8 step analogue sequencer and SSM2044 filter board ( all banana jack connectors and pots in a bronze metal box.. :)

Makes me wonder if it would be possible to synthesize the 76477 chip using the papilio! That would be something I'd like to do...

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  • 2 months later...

I think it has been summed up fairly well here. The schematic entry is a great route for beginners and makes it dead easy to get something up and running. For a very visual person like myself, I found it to be an invaluable way to break the ice and familiarize myself with the tools and concepts. It is possible to implement fairly complex designs via schematic entry, but as has been said, it starts to get very tedious. What I've been doing is transitioning more and more towards VHDL, using a mix of the two methods. One of the really cool things about all this is that it's possible to almost seemlessly mix and match HDLs within the same project, since unlike a programming language, your code is describing the way hardware is wired up rather than executing instructions.


Schematic is great for simple stuff like you would put into a small to midsized CPLD, but once you get to something that really utilizes a FPGA, you will quickly find that it gets unbearably tedious and unweildy. A pencil & paper to sketch and visualize the logic as you write the HDL code can be a lot less tedious than the schematic editor.

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