What a huge amount of fun this is.

[bithead]

I cannot believe the amount of fun I've had since finding the Papilio platform after I dipped my toe into the Arduino world.

 

This probably isn't the best place to post this, but I'll put it here to begin with -- my current adventures are with the Papilio Pro, so this is the forum I read the most.

 

My current project involves creating a system revolving around the J1 Forth core, since I've had a fascination with Forth for a long time, and the idea of a core designed to support Forth has always fascinated me.  

 

What I have at the moment is the J1 core running on the Papilio Pro (and the Papilio One), connected to the serial line that talks to the USB on the board. I'm using the UART provided by Xilinx (that you, Jack, for posting your tutorial on using those, it made implementation a lot easier than it could have been). In the process, I added the ability to sleep the processor if it needs to wait for i/o on the way in, or if it's about to overrun the output fifo on transmit. Between the two of those additions, the serial i/o became very relaible.

 

I'm planning on putting the code up on Github. It's actually already up there, but private, since I realized I've got Xilinx code that I cannot distribute as part of the project, I'll take those out before I publish.

 

Right now I'm trying to track down a possible bug in the system (it's in my code, the cross compiler, or in the core)... I've run into some annoyances there (see another post I made previously about BMM files).  Once I have that down, the plan is to move in the following direction:

 

1. SDRAM access -- Make the J1 core interface with the SDRAM on the Pro.

 

2. Multicore -- using Chuck Moore's c18 based chips as an example, I'd like to explore the idea of multiple Forth cores all talking to each other.

 

3. Complete Mini-System -- I realized that the Arcade MegaWing has almost everything needed for a small computer system. PS2 to connect a keyboard and mouse, VGA as an output -- I'm only missing mass storage, but I'll figure out a way around that (hint -- a megawing with PS2 connectors, VGA, audio out, and an SD Card interface would be purchased, by me, almost immediately).

 

4. Somewhere else -- it's always possible that something shiny will catch my eye and I'll go in a different direction.

 

It blows me away that with the Papilio platform and the free tools provided by Xilinx, a hobbiest such as myself can actually play with processor design. When I first went to college (mid 80's), the only way to really do processor design was to get hired by a place that was already doing processor design, since you needed someone who could bankroll the silicon foundry part of things. Sure, you could maybe play around with programmable ASICs, but once you burned them with your configuration, that was it. Either way, it was expensive.

 

So, thank you Jack and the Gadget Factory for bringing this stuff to market. Thanks to Hamster for putting out the material that got me successfully started along this path. Perhaps I'll be able to give back something.

 

[Jack Gassett]

Thank you for the awesome encouraging post. It's great to hear about what people are working on.

 

I cannot believe the amount of fun I've had since finding the Papilio platform after I dipped my toe into the Arduino world.

 

This probably isn't the best place to post this, but I'll put it here to begin with -- my current adventures are with the Papilio Pro, so this is the forum I read the most.

 

My current project involves creating a system revolving around the J1 Forth core, since I've had a fascination with Forth for a long time, and the idea of a core designed to support Forth has always fascinated me.  

 

What I have at the moment is the J1 core running on the Papilio Pro (and the Papilio One), connected to the serial line that talks to the USB on the board. I'm using the UART provided by Xilinx (that you, Jack, for posting your tutorial on using those, it made implementation a lot easier than it could have been). In the process, I added the ability to sleep the processor if it needs to wait for i/o on the way in, or if it's about to overrun the output fifo on transmit. Between the two of those additions, the serial i/o became very relaible.

 

I'm planning on putting the code up on Github. It's actually already up there, but private, since I realized I've got Xilinx code that I cannot distribute as part of the project, I'll take those out before I publish.

 

Right now I'm trying to track down a possible bug in the system (it's in my code, the cross compiler, or in the core)... I've run into some annoyances there (see another post I made previously about BMM files).  Once I have that down, the plan is to move in the following direction:

 

1. SDRAM access -- Make the J1 core interface with the SDRAM on the Pro.

 

2. Multicore -- using Chuck Moore's c18 based chips as an example, I'd like to explore the idea of multiple Forth cores all talking to each other.

 

3. Complete Mini-System -- I realized that the Arcade MegaWing has almost everything needed for a small computer system. PS2 to connect a keyboard and mouse, VGA as an output -- I'm only missing mass storage, but I'll figure out a way around that (hint -- a megawing with PS2 connectors, VGA, audio out, and an SD Card interface would be purchased, by me, almost immediately).

There is a new design that started out as the Arcade MegaWing upgrade but will rather be pitched as an embedded systems MegaWing. It has SD Card, 2-PS/2, VGA, micro-joystick, and a snappable section with two joystick ports. The snappable section can be snapped off to free up a 16 bit Wing slot. Hopefully we will see it available in the next month or so, I just need to build some prototypes for the manufacturers now.

 

 

4. Somewhere else -- it's always possible that something shiny will catch my eye and I'll go in a different direction.

 

It blows me away that with the Papilio platform and the free tools provided by Xilinx, a hobbiest such as myself can actually play with processor design. When I first went to college (mid 80's), the only way to really do processor design was to get hired by a place that was already doing processor design, since you needed someone who could bankroll the silicon foundry part of things. Sure, you could maybe play around with programmable ASICs, but once you burned them with your configuration, that was it. Either way, it was expensive.

 

So, thank you Jack and the Gadget Factory for bringing this stuff to market. Thanks to Hamster for putting out the material that got me successfully started along this path. Perhaps I'll be able to give back something.

 

 

Thank you for your support!

Jack.

[Hans]

bithead,

 

please let us know when you're sharing your Forth core on github.  I have been toying around with a Forth running on John Kent's System09 in a Spartan3 for a while (https://github.com/hanshuebner/rekonstrukt), and I like the idea of having an interactive system to play with very much.

 

Thanks!

Hans

[alvieboy]

Which Forth compiler are you using ? Is it generic enough to work on any other platform ?

 

I'm asking this because ZPU (ZPUino and all the variants) are stack processors, and probably getting Forth to run nicely on them should be rather quick.

 

Alvie

[Hans]

Alvie,

 

the CPU I have been toying around with is a MC6809 clone (http://members.optushome.com.au/jekent/system09/).  J1 (http://www.excamera.com/sphinx/fpga-j1.html) is tailored more directly towards supporting Forth.  Writing a Forth for the ZPU should not be very hard, and it would be kind of a nice thing as ZPU supports Wishbone (System09 does not, and J1 does not seem to support it either).

 

The Forth (called MaisForth) that I've been using on System09 is not very generic.  It is cross compiled with WinForth and I mostly used it in a black box fashion - I just ported it from the original mc6809 based hardware (the "MaisKastje") to System09.  It assumes quite a lot about the CPU though, so I don't think that porting it to the 32 bit ZPU would make a lot of sense.

 

At this point, I'll probably stick to GCC based development for RetroCade Synth hacking, but I'd like to play with J1 a bit, too.

 

Cheers,

Hans

[bithead]

Alvie: I've been using the J1 forth cpu from here: http://excamera.com/sphinx/fpga-j1.html

 

I have it running, and I have it talking to a serial console, but I am quite far away from having an interactive Forth experience running on the cpu. What I have is a gforth-based cross compiler that spits out code that I can load into the CPU (right now I'm using a trick to get the code in, and it is in no way a shortcut, I end up having to resynthesize everything).  I've been able to prove to myself that the system is running, but not much beyond that. Getting the outer Forth interpreter running (that's the command processor most people interact with) means rolling up my sleeves and writing Forth.

 

I've also contemplated using the b16 processor from here: http://bernd-paysan.de/b16.html

 

...either the b16 or the b16-small (I'd probably do the b16 as it seems small enough). My hesitancy there is because I don't know of any working cross compilers for that chip, and the J1 had one that worked out of the box.

 

I didn't realize that the ZPU was a stack machine.  I'm going to have to read up on it.

[Jack Gassett]

You might want to take a look at this thread. I think someone already got interactive Forth running on the Papilio, might save you some time.

 

Jack.

[bithead]

Actually, I did see that thread early on. That was one of the motivations -- someone else got it to work, so I should be able to.

 

I'm a bit of a masochist, it seems.

 

The root of this comes from college -- a friend of mine, while he was in high school (we both graduated in 1983, so you understand the time frame) wrote and sold a Forth interpreter for the Apple II.  I thought that was impressive.  Ever since then, it has been in my brain that I wanted to roll my own Forth sometime.  So this is what I'm doing, although I'm starting out a little lower by actually working on the hardware level first.

 

I'm not opposed to stealing code when I find it useful, but I also want to do as much myself as I can.  Like I said, I'm a masochist.

 

Heck, that's why I'm playing with FPGAs rather than just getting a processor and starting there.

[ben]

good luck and have fun -- being a bit of a masochist myself, i went for the "who needs a stock cross compiler when you can make your own" option, which definitely was not a good choice for the comfort of development !

[spygadget]

hey if we are taking to our work as fun then we are not feeling bore for work and we can easily and nicely can finish our work

[cybertramp]

Bithead,

 

Very cool project. I'm working on a similar J1 project myself. Does/will yours use subroutine threading? Just curious. I chose to go the STC route before I knew it was called STC! It just seemed like the most straightforward way to go.