MIPS core on Papilio


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Hi community,

I had been playing with a MIPS core from Dossmatik (www.dossmatik.de) for a while and managed to squeeze it to <50% of the Papilio One with the Sp3 250k. The beast now runs stable at 64 MHz (using DLL 2x) and can be debugged using a mips-elf-gdb directly through JTAG via the USB port using In Circuit Emulation tricks. Turns out to be a nice platform for DSP stuff so far.

It turned out to be a little complicated project, and there's almost no documentation and source ready, but I thought I'd give it a go and let you know what else could be done with the Papilio.

(Pics and some resource info: http://tech.section5.ch/news/?p=251)

Has anyone else tried other MIPS cores on the Papilio?

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This is great. :)

Sounds like 50% of the P1 250K leaves plenty of room for other stuff and the most exciting thing is the debugging capability. I just read the blog post you linked to above and I'm super excited about the debugging capabilities you are talking about. As I've been working on the RetroCade Synth code I've been wishing for debug ability. :)

Does the debugger work with the FT2232 JTAG or is a separate jtag debugger required?

Let me know if there is anything I can do to support your efforts or support your demo at embedded world. More hardware etc.


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Hi Jack,

yeah, the debugging is what seems to be lacking on most of the soft CPUs. I don't want to miss the luxury again :-)

The debugger proxy works just with the FT2232 on the Papilio, no extra HW. It's a bit quirky though.

It also works for the ZPU (Zealot).

I think Alvaro has been doing something similar, by using the USER1 and USER2 chains from the Xilinx BSCAN_SPARTAN3 primitive.

Thanks a lot for the offer about hardware. For now, I guess we're pretty set. I got a Papilio for the Author of this MIPS core as well, I hope this will boost some development beginning of next year. I'll try to convince him to make it a community project. Anyhow, someone could look at integrating the ICE (In Circuit Emulation) into the architecture you use for your Synth project (AVR? Sorry for my ignorance). Basically, any processor able to handle exceptions should need only a few little intrusive changes to implement ICE.

The code can be grabbed from some ZPU experimental tree and the TAP (test access port) for Spartan3 could be opensourced as well. Let's see what happens next year..development is expected to walk kinda slow on this lane (limited free time resources....)


- Martin

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Hey Alvie,

That was the completely cut down config I used for testing, which is not of real practical use. There's no external RAM on this one.

This is more realistic (and also includes some DMA logic, thus little higher gate count):

Selected Device : 3s250evq100-5

Number of Slices: 1357 out of 2448 55%

Number of Slice Flip Flops: 1108 out of 4896 22%

Number of 4 input LUTs: 2585 out of 4896 52%

Number of IOs: 15

Number of bonded IOBs: 15 out of 66 22%

Number of BRAMs: 8 out of 12 66%

Number of GCLKs: 5 out of 24 20%

Number of DCMs: 1 out of 4 25%

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:) Still, only a few BRAM used, and not many IO.

If i recall, MIPS has 32-bit wide instructions, so it really needs memory to bootstrap even simple applications.

I'm assuming you're only trying synthesis here, not actually a full working system. What are your plans for that ? Use only internal RAM or use external (or both) ?



(btw, care to share the full MAP report ?)

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Hi Alvie,

it is in fact a working system (see link above, the rainbow is scrolled over the TFT by the MIPS), just not doing very much, so internal RAM is ok for now on the Papilio. There are other MIPS clones (like plasma, ion) which have cache, external memory, etc. but they also consume way more resources. I'm actually evaluating it as host processor for some image processing core (which is currently initialized by the ZPU), but this again runs on a Spartan6. The Papilio is just a cool and simple to debug demo platform for now.


- Martin

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