veqtor Posted October 19, 2012 Report Share Posted October 19, 2012 The C64 still needs a SVF for it to be complete, but I found one at the fpga.synth.net wiki:http://fpga.synth.ne...n=FPGASynth.SVFUnfortunatly it's in verilog so I wouldn't know how to work it into the netsid code.Looking at the block diagram it seems to me it's just about right. Very little is known about the C64 svf, except it was vanillla and probably done with CMOS inverters and used a crude R2R dac as a variable resistor to control the cutoff. Putting more effort into emulation of that particular svf design could yield somewhat more authentic results but I doubt there'd be much of a difference tbh, what could account for some of character is the output dac from the chip and also the multiplying dac after the filter. Any DC offset on the pre-filter dac would make the filter do weird things while sweeping etc.looks like the bp and hp outs aren't implemented yet, but that should be easy enough...edit: just to clarify how to get the other outputs:HP out could be grabbed from this part: 3'd0: begin mA <= f; mB <= ((DataIn << 18) - mP - z2) >>> 17; endwhere HP is being sent to mB (multiplier b input). Take out that step and send it to a HP register besides sending it to mB.BP out would be pulled from here: 3'd1: begin mA <= f; mB <= z1 >>> 17; z1 <= mP + z1; endBesides sending mP + z1 back into z1, write it to a BP register.All that is left then is to make a MUX that sums the various outs so that notch (LP+HP) and such variants can be created.I hope this can be of some help! Quote Link to comment Share on other sites More sharing options...
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